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Displaying 1-10 out of 10 total
In-network Monitoring and Control Policy for DVFS of CMP Networks-on-Chip and Last Level Caches
Found in: Networks-on-Chip, International Symposium on
By Xi Chen,Zheng Xu,Hyungjun Kim,Paul Gratz,Jiang Hu,Michael Kishinevsky,Umit Ogras
Issue Date:May 2012
pp. 43-50
In chip design today and for a foreseeable future, on-chip communication is not only a performance bottleneck but also a substantial power consumer. This work focuses on employing dynamic voltage and frequency scaling (DVFS) policies for networks-on-chip (...
xMAS: Quick Formal Modeling of Communication Fabrics to Enable Verification
Found in: IEEE Design and Test of Computers
By Satrajit Chatterjee,Mike Kishinevsky,Umit Ogras
Publication Date: June 2011
pp. N/A
Although communication fabrics at the microarchitectural level are mainly composed of standard primitives such as queues and arbiters, to get an executable model one has to connect these primitives with glue logic to complete the description. In this paper...
System interconnect design exploration for embedded MPSoCs
Found in: System Level Interconnect Prediction, International Workshop on
By Chen-Ling Chou,Radu Marculescu,Umit Ogras,Satrajit Chatterjee,Michael Kishinevsky,Dmitrii Loukianov
Issue Date:June 2011
pp. 1-8
This paper presents a new approach for system interconnect design exploration of application-specific multi-processor systems-on-chip (MPSoCs). As a novel contribution, we develop an analytical model for network-based communication design space exploration...
Physical-Aware Link Allocation and Route Assignment for Chip Multiprocessing
Found in: Networks-on-Chip, International Symposium on
By Nikita Nikitin, Satrajit Chatterjee, Jordi Cortadella, Mike Kishinevsky, Umit Ogras
Issue Date:May 2010
pp. 125-134
The architecture definition, design, and validation of the interconnect networks is a key step in the design of modern on-chip systems. This paper proposes a mathematical formulation of the problem of simultaneously defining the topology of the network and...
Towards Open Network-on-Chip Benchmarks
Found in: Networks-on-Chip, International Symposium on
By Cristian Grecu, Andre Ivanov, Partha Pande, Axel Jantsch, Erno Salminen, Umit Ogras, Radu Marculescu
Issue Date:May 2007
pp. 205
Measuring and comparing performance, cost, and other features of advanced communication architectures for complex multi core/multiprocessor systems on chip is a significant challenge which has hardly been addressed so far. <p>This document outlines t...
Dimensionality Reduction and Similarity Computation by Inner-Product Approximations
Found in: IEEE Transactions on Knowledge and Data Engineering
By Ömer Egecioglu, Hakan Ferhatosmanoglu, Umit Ogras
Issue Date:June 2004
pp. 714-726
<p><b>Abstract</b>—As databases increasingly integrate different types of information such as multimedia, spatial, time-series, and scientific data, it becomes necessary to support efficient retrieval of multidimensional data. Both the di...
Constrained Energy Optimization in Heterogeneous Platforms using Generalized Scaling Models
Found in: IEEE Computer Architecture Letters
By Ujjwal Gupta,Umit Ogras
Issue Date:May 2014
pp. 1
Platform energy consumption and responsiveness are two major considerations for mobile systems since they determine the battery life and user satisfaction, respectively. We first present models for power consumption, response time and energy consumption of...
In-network monitoring and control policy for DVFS of CMP networks-on-chip and last level caches
Found in: ACM Transactions on Design Automation of Electronic Systems (TODAES)
By Michael Kishinevsky, Paul Gratz, Xi Chen, Zheng Xu, Hyungjun Kim, Jiang Hu, Umit Ogras
Issue Date:October 2013
pp. 1-21
In chip design today and for a foreseeable future, the last-level cache and on-chip interconnect is not only performance critical but also a substantial power consumer. This work focuses on employing dynamic voltage and frequency scaling (DVFS) policies fo...
Design and optimization of communication fabrics: an industrial perspective
Found in: Proceedings of the International Workshop on System Level Interconnect Prediction (SLIP '12)
By Michael Kishinevsky, Umit Ogras
Issue Date:June 2012
pp. 19-19
Design of SoCs as well as general purpose client and server systems rely increasingly on integrating available IP cores such as processing cores, accelerators and memory blocks to improve energy efficiency, reduce time to market and/or cost. As a result, t...
Technology-driven limits on DVFS controllability of multiple voltage-frequency island designs: a system-level perspective
Found in: Proceedings of the 46th Annual Design Automation Conference (DAC '09)
By Diana Marculescu, Radu Marculescu, Siddharth Garg, Umit Ogras
Issue Date:July 2009
pp. 818-821
In this paper, we consider the case of network-on-chip (NoC) based multiple-processor systems-on-chip (MPSoCs) implemented using multiple voltage and frequency islands (VFIs) that rely on fine-grained dynamic voltage and frequency scaling (DVFS) for run-ti...