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Displaying 1-20 out of 20 total
A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience
Found in: IEEE Micro
By Veit B. Kleeberger,Christina Gimmler-Dumont,Christian Weis,Andreas Herkersdorf,Daniel Mueller-Gritschneder,Sani R. Nassif,Ulf Schlichtmann,Norbert Wehn
Issue Date:July 2013
pp. 46-55
Highly scaled technologies at and beyond the 22-nm node exhibit increased sensitivity to various scaling-related problems that conspire to reduce the overall reliability of integrated circuits and systems. In prior technology nodes, the assumption was that...
 
Schedulability Analysis for Processors with Aging-Aware Autonomic Frequency Scaling
Found in: 2012 IEEE 18th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2012)
By Alejandro Masrur,Philipp Kindt,Martin Becker,Samarjit Chakraborty,Veit Kleeberger,Martin Barke,Ulf Schlichtmann
Issue Date:August 2012
pp. 11-20
With the rapid progress in semiconductor technology and the shrinking of device geometries, the resulting processors are increasingly becoming prone to effects like aging and soft errors. As a processor ages, its electrical characteristics degrade, i.e., t...
 
Control-Flow-Driven Source Level Timing Annotation for Embedded Software Models on Transaction Level
Found in: Digital Systems Design, Euromicro Symposium on
By Daniel Mueller-Gritschneder,Kun Lu,Ulf Schlichtmann
Issue Date:September 2011
pp. 600-607
Instrumented software models feature a combination of software functionality as well as timing information to model execution times on embedded processors. They aim to replace instruction set simulators in virtual prototypes (VP) of embedded systems to imp...
 
Aging analysis of circuit timing considering NBTI and HCI
Found in: On-Line Testing Symposium, IEEE International
By Dominik Lorenz, Georg Georgakos, Ulf Schlichtmann
Issue Date:June 2009
pp. 3-8
We present an aging analysis flow able to calculate the degraded circuit timing. To the best of our knowledge it is the first approach on gate level so far capable of analyzing the impact of the two dominant drift-related aging effects - NBTI and HCI - on ...
 
Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions
Found in: Computer-Aided Design, International Conference on
By Martin Strasser, Michael Eick, Helmut Grab, Ulf Schlichtmann, Frank M. Johannes
Issue Date:November 2008
pp. 306-313
The analog placement algorithm Plantage, presented in this paper, generates placements for analog circuits with comprehensive placement constraints. Plantage is based on a hierarchically bounded enumeration of basic building blocks, using B*-trees. The pra...
 
Sizing Rules for Bipolar Analog Circuit Design
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Tobias Massier, Helmut Graeb, Ulf Schlichtmann
Issue Date:March 2008
pp. 140-145
This paper presents sizing rules for basic building blocks in analog bipolar circuit design. Sizing rules efficiently capture design knowledge on the technology-specific level of transistor-pair groups. This reduces the effort for and improves the resultin...
 
Pareto-Front Computation and Automatic Sizing of CPPLLs
Found in: Quality Electronic Design, International Symposium on
By Jun Zou, Daniel Mueller, Helmut Graeb, Ulf Schlichtmann
Issue Date:March 2007
pp. 481-486
A comprehensive performance space exploration on system level offers designers a fast way to get insight into the capability of the whole system for a given technology. We consider a charge-pump phase-locked loop (CPPLL) system. In this paper performance s...
 
Design Methodology Innovations Address Manufacturing Technology Challenges: Power and Performance
Found in: Digital Systems Design, Euromicro Symposium on
By Ulf Schlichtmann
Issue Date:September 2004
pp. 52-59
Semiconductor design has benefited tremendously from process technology scaling in the past, especially for power consumption and performance. This era is coming to an end. Continued improvement in these key metrics requires even more innovation in design ...
 
Systems Are Made from Transistors: UDSM Technology Creates New Challenges for Library and IC Development
Found in: Digital Systems Design, Euromicro Symposium on
By Ulf Schlichtmann
Issue Date:September 2002
pp. 2
The progress of silicon process technology relentlessly marches on. Moore's law still holds, the number of transistors that can be integrated on an IC doubles approximately every 18 months. The inability of system designs to keep up with this ever increasi...
   
Fast Power Estimation of Large Circuits
Found in: IEEE Design and Test of Computers
By Peter H. Schneider, Ulf Schlichtmann, Bernd Wurth
Issue Date:March 1996
pp. 70-78
<p>Logic-level circuit optimization for low power requires efficient estimation of the power consumed by the resulting circuit. In CMOS, the power consumption depends on the number of transitions occurring on the signals internal to a circuit. We int...
 
An Analysis of Industrial SRAM Test Results - A Comprehensive Study on Effectiveness and Classification of March Test Algorithms
Found in: IEEE Design & Test
By Michael Linder,Alfred Eder,Ulf Schlichtmann,Klaus Oberlander
Issue Date:August 2013
pp. 1
Modern microcontroller devices contain large numbers of embedded SRAM memories. Especially microcontrollers for automotive applications are highly safety critical and so are their embedded memories. Zero defect density of memories is an essential safety re...
 
Reliability challenges for electric vehicles: from devices to architecture and systems software
Found in: Proceedings of the 50th Annual Design Automation Conference (DAC '13)
By Samarjit Chakraborty, Ulf Schlichtmann
Issue Date:May 2013
pp. 1-9
Today, modern high-end cars have close to 100 electronic control units (ECUs) that are used to implement a variety of applications ranging from safety-critical control to driver assistance and comfort-related functionalities. The total sum of these applica...
     
Automatic generation of hierarchical placement rules for analog integrated circuits
Found in: Proceedings of the 19th international symposium on Physical design (ISPD '10)
By Helmut E. Graeb, Martin Strasser, Michael Eick, Ulf Schlichtmann
Issue Date:March 2010
pp. 47-54
This paper presents a new method to automatically generate hierarchical placement rules, which are crucial for a successful analog placement. The netlist, a library of building blocks and a symmetry analysis are the basis to determine a constraint requirem...
     
Timing model extraction for sequential circuits considering process variations
Found in: Proceedings of the 2009 International Conference on Computer-Aided Design (ICCAD '09)
By Bing Li, Ning Chen, Ulf Schlichtmann
Issue Date:November 2009
pp. 336-343
As semiconductor devices continue to scale down, process variations become more relevant for circuit design. Facing such variations, statistical static timing analysis is introduced to model variations more accurately so that the pessimism in traditional w...
     
Abacus: fast legalization of standard cell circuits with minimal movement
Found in: Proceedings of the 2008 international symposium on Physical design (ISPD '08)
By Frank M. Johannes, Peter Spindler, Ulf Schlichtmann
Issue Date:April 2008
pp. 4-4
Standard cell circuits consist of millions of standard cells, which have to be aligned overlap-free to the rows of the chip. Placement of these circuits is done in consecutive steps. First, a global placement is obtained by roughly spreading the cells on t...
     
Sizing rules for bipolar analog circuit design
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '08)
By Helmut Graeb, Tobias Massier, Ulf Schlichtmann
Issue Date:March 2008
pp. 1-30
This paper presents sizing rules for basic building blocks in analog bipolar circuit design. Sizing rules efficiently capture design knowledge on the technology-specific level of transistor-pair groups. This reduces the effort for and improves the resultin...
     
Trade-off design of analog circuits using goal attainment and "Wave Front" sequential quadratic programming
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '07)
By Daniel Mueller, Helmut Graeb, Ulf Schlichtmann
Issue Date:April 2007
pp. 75-80
One of the main tasks in analog design is the sizing of the circuit parameters, such as transistor lengths and widths, in order to obtain optimal circuit performances, such as high gain or low power consumption. In most cases one performance can only be op...
     
A CPPLL hierarchical optimization methodology considering jitter, power and locking time
Found in: Proceedings of the 43rd annual conference on Design automation (DAC '06)
By Daniel Mueller, Helmut Graeb, Jun Zou, Ulf Schlichtmann
Issue Date:July 2006
pp. 19-24
In this paper, a hierarchical optimization methodology for charge pump phase-locked loops (CPPLLs) is proposed. It has the following features: 1) A comprehensive and efficient behavioral modeling of the PLL enables fast simulations and includes the importa...
     
Deterministic approaches to analog performance space exploration (PSE)
Found in: Proceedings of the 42nd annual conference on Design automation (DAC '05)
By Daniel Mueller, Guido Stehr, Helmut Graeb, Ulf Schlichtmann
Issue Date:June 2005
pp. 869-874
Performance space exploration (PSE) determines the range of feasible performance values of a circuit block for a given topology and technology. In this paper, we present two deterministic approaches for PSE. One approximates the feasible performance space ...
     
Functional multiple-output decomposition with application to technology mapping for lookup table-based FPGAs
Found in: ACM Transactions on Design Automation of Electronic Systems (TODAES)
By Bernd Wurth, Klaus Eckl, Kurt J. Antreich, Ulf Schlichtmann
Issue Date:January 1996
pp. 313-350
Functional decomposition is an important technique for technology mapping to look up table-based FPGA architectures. We present the theory of and a novel approach to functional disjoint decomposition of multiple-output functions, in which common subfunctio...
     
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