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Displaying 1-18 out of 18 total
Compiler Directed Early Register Release
Found in: Parallel Architectures and Compilation Techniques, International Conference on
By Timothy M. Jones, Michael F.P. O'Boyle, Jaume Abella, Antonio Gonzalez, O¢guz Ergin
Issue Date:September 2005
pp. 110-122
<p>This paper presents a novel compiler directed technique to reduce the register pressure and power of the register file by releasing registers early. The compiler identifies registers that will only be read once and renames them to different logica...
 
An Empirical Architecture-Centric Approach to Microarchitectural Design Space Exploration
Found in: IEEE Transactions on Computers
By Christophe Dubach,Timothy M. Jones,Michael F.P. O'Boyle
Issue Date:October 2011
pp. 1445-1458
The microarchitectural design space of a new processor is too large for an architect to evaluate in its entirety. Even with the use of statistical simulation, evaluation of a single configuration can take an excessive amount of time due to the need to run ...
 
Link-time optimization for power efficiency in a tagless instruction cache
Found in: Code Generation and Optimization, IEEE/ACM International Symposium on
By Timothy M. Jones, Sandro Bartolini, Jonas Maebe, Dominique Chanet
Issue Date:April 2011
pp. 32-41
The instruction cache is a critical component in any microprocessor. It must have high performance to enable fetching of instructions on every cycle. However, current designs waste a large amount of energy on each access as tags and data banks from all cac...
 
A Predictive Model for Dynamic Microarchitectural Adaptivity Control
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Christophe Dubach, Timothy M. Jones, Edwin V. Bonilla, Michael F.P. O'Boyle
Issue Date:December 2010
pp. 485-496
Adaptive micro architectures are a promising solution for designing high-performance, power-efficient microprocessors. They offer the ability to tailor computational resources to the specific requirements of different programs or program phases. They have ...
 
Helix: Making the Extraction of Thread-Level Parallelism Mainstream
Found in: IEEE Micro
By Simone Campanoni,Timothy M. Jones,Glenn Holloway,Gu-Yeon Wei,David Brooks
Issue Date:July 2012
pp. 8-18
Improving system performance increasingly depends on exploiting microprocessor parallelism, yet mainstream compilers still don&amp;#x0027;t parallelize code automatically. Helix automatically parallelizes general-purpose programs without requiring any ...
 
Cooperative partitioning: Energy-efficient cache partitioning for high-performance CMPs
Found in: High-Performance Computer Architecture, International Symposium on
By Karthik T. Sundararajan,Vasileios Porpodas,Timothy M. Jones,Nigel P. Topham,Bjorn Franke
Issue Date:February 2012
pp. 1-12
Intelligently partitioning the last-level cache within a chip multiprocessor can bring significant performance improvements. Resources are given to the applications that can benefit most from them, restricting each core to a number of logical cache ways. H...
 
Beforehand Migration on D-NUCA Caches
Found in: Parallel Architectures and Compilation Techniques, International Conference on
By Javier Lira,Timothy M. Jones,Carlos Molina,Antonio Gonz´lez
Issue Date:October 2011
pp. 197-198
Determining the best placement for data in the NUCA cache at any particular moment during program execution is crucial for exploiting the benefits that this architecture provides. Dynamic NUCA (D-NUCA) allows data to be mapped to multiple banks within the ...
 
Instruction Cache Energy Saving Through Compiler Way-Placement
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Timothy M. Jones, Sandro Bartolini, Bruno De Bus, John Cavazos, Michael F.P. O'Boyle
Issue Date:March 2008
pp. 1196-1201
Fetching instructions from a set-associative cache in an embedded processor can consume a large amount of energy due to the tag checks performed. Recent proposals to address this issue involve predicting or memoizing the correct way to access. However, the...
 
Software Directed Issue Queue Power Reduction
Found in: High-Performance Computer Architecture, International Symposium on
By Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González
Issue Date:February 2005
pp. 144-153
The issue logic of a superscalar processor dissipates a large amount of static and dynamic power. Furthermore, its power density makes it a hot-spot requiring expensive cooling systems and additional packaging.<div></div> In this paper we prese...
 
HELIX-RC: An architecture-compiler co-design for automatic parallelization of irregular programs
Found in: 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)
By Simone Campanoni,Kevin Brownell,Svilen Kanev,Timothy M. Jones,Gu-Yeon Wei,David Brooks
Issue Date:June 2014
pp. 217-228
Data dependences in sequential programs limit parallelization because extracted threads cannot run independently. Although thread-level speculation can avoid the need for precise dependence analysis, communication overheads required to synchronize actual d...
   
Dynamic microarchitectural adaptation using machine learning
Found in: ACM Transactions on Architecture and Code Optimization (TACO)
By Christophe Dubach, Edwin V. Bonilla, Timothy M. Jones
Issue Date:December 2013
pp. 1-28
Adaptive microarchitectures are a promising solution for designing high-performance, power-efficient microprocessors. They offer the ability to tailor computational resources to the specific requirements of different programs or program phases. They have t...
     
Energy-efficient cache partitioning for future CMPs
Found in: Proceedings of the 21st international conference on Parallel architectures and compilation techniques (PACT '12)
By Karthik T. Sundararajan, Nigel P. Topham, Timothy M. Jones
Issue Date:September 2012
pp. 465-466
The demand for high performance computing systems requires processor vendors to increase the number of cores per chip multiprocessor (CMP). However, as their number grows, the core-to-way ratio in the last level cache (LLC) increases, presenting problems t...
     
Exploring and Predicting the Effects of Microarchitectural Parameters and Compiler Optimizations on Performance and Energy
Found in: ACM Transactions on Embedded Computing Systems (TECS)
By Christophe Dubach, Michael F. P. O’Boyle, Timothy M. Jones
Issue Date:June 2012
pp. 1-24
Embedded processor performance is dependent on both the underlying architecture and the compiler optimizations applied. However, designing both simultaneously is extremely difficult to achieve due to the time constraints designers must work under. Therefor...
     
The migration prefetcher: Anticipating data promotion in dynamic NUCA caches
Found in: ACM Transactions on Architecture and Code Optimization (TACO)
By Javier Lira, Timothy M. Jones, Antonio Gonzalez, Carlos Molina
Issue Date:January 2012
pp. 1-20
The exponential increase in multicore processor (CMP) cache sizes accompanied by growing on-chip wire delays make it difficult to implement traditional caches with a single, uniform access latency. Non-Uniform Cache Architecture (NUCA) designs have been pr...
     
A reconfigurable cache architecture for energy efficiency
Found in: Proceedings of the 8th ACM International Conference on Computing Frontiers (CF '11)
By Karthik T. Sundararajan, Nigel Topham, Timothy M. Jones
Issue Date:May 2011
pp. 1-2
On-chip caches often consume a significant fraction of the total processor energy budget. Allowing adaptation to the running workload can significantly lower their energy consumption. In this paper, we present a novel Set and way Management cache Architect...
     
Portable compiler optimisation across embedded programs and microarchitectures using machine learning
Found in: Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (Micro-42)
By Christophe Dubach, Edwin V. Bonilla, Grigori Fursin, Michael F. P. O'Boyle, Timothy M. Jones
Issue Date:December 2009
pp. 78-88
Building an optimising compiler is a difficult and time consuming task which must be repeated for each generation of a microprocessor. As the underlying microarchitecture changes from one generation to the next, the compiler must be retuned to optimise spe...
     
Exploring and predicting the architecture/optimising compiler co-design space
Found in: Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems (CASES '08)
By Christophe Dubach, Michael F.P. O'Boyle, Timothy M. Jones
Issue Date:October 2008
pp. 79-79
Embedded processor performance is dependent on both the underlying architecture and the compiler optimisations applied. However, designing both simultaneously is extremely difficult to achieve due to the time constraints designers must work under. Therefor...
     
Instruction cache energy saving through compiler way-placement
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '08)
By Bruno De Bus, John Cavazos, Michael F. P. O'Boyle, Sandro Bartolini, Timothy M. Jones
Issue Date:March 2008
pp. 1-30
Fetching instructions from a set-associative cache in an embedded processor can consume a large amount of energy due to the tag checks performed. Recent proposals to address this issue involve predicting or memoizing the correct way to access. However, the...
     
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