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Displaying 1-4 out of 4 total
Cache-Conscious Thread Scheduling for Massively Multithreaded Processors
Found in: IEEE Micro
By Timothy G. Rogers,Mike O'Connor,Tor M. Aamodt
Issue Date:May 2013
pp. 78-85
Highly multithreaded architectures introduce another dimension to fine-grained hardware cache management. The order in which the system's threads issue instructions can significantly impact the access stream seen by the caching system. This article studies...
 
Characterizing and evaluating a key-value store application on heterogeneous CPU-GPU systems
Found in: Performance Analysis of Systems and Software, IEEE International Symmposium on
By Tayler H. Hetherington,Timothy G. Rogers,Lisa Hsu,Mike O'Connor,Tor M. Aamodt
Issue Date:April 2012
pp. 88-98
The recent use of graphics processing units (GPUs) in several top supercomputers demonstrate their ability to consistently deliver positive results in high-performance computing (HPC). GPU support for significant amounts of parallelism would seem to make t...
 
Cache-Conscious Wavefront Scheduling
Found in: 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
By Timothy G. Rogers,Mike OConnor,Tor M. Aamodt
Issue Date:December 2012
pp. 72-83
This paper studies the effects of hardware thread scheduling on cache management in GPUs. We propose Cache-Conscious Wave front Scheduling (CCWS), an adaptive hardware mechanism that makes use of a novel intra-wave front locality detector to capture locali...
 
Divergence-aware warp scheduling
Found in: Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-46)
By Mike O'Connor, Timothy G. Rogers, Tor M. Aamodt
Issue Date:December 2013
pp. 99-110
This paper uses hardware thread scheduling to improve the performance and energy efficiency of divergent applications on GPUs. We propose Divergence-Aware Warp Scheduling (DAWS), which introduces a divergence-based cache footprint predictor to estimate how...
     
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