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Displaying 1-50 out of 74 total
Modeling Yield, Cost, and Quality of a Spare-Enhanced Multicore Chip
Found in: IEEE Transactions on Computers
By Saeed Shamshiri,Kwang-Ting (Tim) Cheng
Issue Date:September 2011
pp. 1246-1259
It becomes increasingly difficult to achieve a high manufacturing yield for multicore chips due to larger chip sizes, higher device densities, and greater failure rates. By adding a limited number of spare cores and wires to replace defective cores and wir...
 
A Promising Alternative to Conventional Silicon
Found in: IEEE Design and Test of Computers
By Jiun-Lang Huang,Kwang-Ting (Tim) Cheng
Issue Date:November 2011
pp. 6
This special issue of Design & Test provides an overview on the challenges, the current practice, and future research directions of design and test of flexible electronics for various applications.
 
Guest Editors' Introduction: Speed Test and Speed Binning for Complex ICs
Found in: IEEE Design and Test of Computers
By Kenneth M. Butler, Kwang-Ting (Tim) Cheng, Li-C. Wang
Issue Date:September 2003
pp. 6-7
No summary available.
 
Guest Editor's Introduction
Found in: IEEE Design and Test of Computers
By Wayne Wei-Ming Dai, Kwang-Ting (Tim) Cheng
Issue Date:October 1993
pp. 7
No summary available.
   
Embedded-Software-Based Approach to Testing Crosstalk-Induced Faults at On-Chip Buses
Found in: VLSI Test Symposium, IEEE
By Wei-Cheng Lai, Jing-Reng Huang, Kwang-Ting (Tim) Cheng
Issue Date:April 2001
pp. 0204
Crosstalk effects on long interconnects are becoming significant for high-speed circuits. This paper addresses the problem of testing crosstalk-induced faults at on-chip buses in system-on-a-chip (SOC) designs. We propose a method to self-test on-chip buse...
 
Test Program Synthesis for Path Delay Faults in Microprocessor Cores
Found in: Test Conference, International
By Wei-Cheng Lai, Angela Krstic, Kwang-Ting (Tim) Cheng
Issue Date:October 2000
pp. 1080
This paper addresses the problem of testing path delay faults in a microprocessor core using its instruction set. We propose to self-test a processor core by running an automatically synthesized test program which can achieve a high path delay fault covera...
 
Functionally Testable Path Delay Faults on a Microprocessor
Found in: IEEE Design and Test of Computers
By Wei-Cheng Lai, Angela Krstic, Kwang-Ting (Tim) Cheng
Issue Date:October 2000
pp. 6-14
We address the problem of testing path delay faults in a microprocessor using instructions. It is observed that a structurally testable path (i.e., a path testable through at-speed scan) in a microprocessor might not be testable by its instructions. This i...
 
On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set
Found in: VLSI Test Symposium, IEEE
By Wei-Cheng Lai, Angela Krstic, Kwang-Ting (Tim) Cheng
Issue Date:May 2000
pp. 15
This paper addresses the problem of testing path delay faults in a microprocessor using instructions. It is observed that a structurally testable path (i.e., a path testable through at-speed scan) in a microprocessor might not be testable by its instructio...
 
Adaptive test selection for post-silicon timing validation: A data mining approach
Found in: 2012 IEEE International Test Conference (ITC)
By Ming Gao,Peter Lisherness,Kwang-Ting (Tim) Cheng
Issue Date:November 2012
pp. 1-7
Test failure data produced during post-silicon validation contain accurate design- and process-specific information about the DUD (design-under-debug). Prior research efforts and industry practice focused on feeding this information back to the design flow...
 
Coverage discounting: A generalized approach for testbench qualification
Found in: High-Level Design, Validation, and Test Workshop, IEEE International
By Peter Lisherness,Kwang-Ting (Tim) Cheng
Issue Date:November 2011
pp. 49-56
In simulation-based validation, the detection of design errors requires both stimulus capable of activating the errors and checkers capable of detecting the behavior as erroneous. Validation coverage metrics tend to address only the sufficiency of a testbe...
 
Robust Circuit Design for Flexible Electronics
Found in: IEEE Design and Test of Computers
By Tsung-Ching Huang,Jiun-Lang Huang,Kwang-Ting (Tim) Cheng
Issue Date:November 2011
pp. 8-15
Editor's note:In this review article, the authors survey several thin-film transistor (TFT) technologies for flexible electronics of the future. The review's focus centers on the reliability issues of these new devices compared to those of classic silicon ...
 
Image-Quality-Driven Metrics for Testing and Calibrating ADC Array in CMOS Imagers: A First Step
Found in: Mixed-Signals, Sensors, and Systems Test Workshop, IEEE 14th International
By Hsiu-Ming Sherman Chang,Kwang-Ting Tim Cheng,Jiun-Lang Huang
Issue Date:May 2011
pp. 29-32
CMOS imagers that consist of a pixel array of image sensors, an analog-to-digital converter (ADC) array, and image signal processors (ISPs) have been widely adopted in various imaging applications. Since the array of ADCs in the imager jointly and concurre...
 
Time-Multiplexed Online Checking
Found in: IEEE Transactions on Computers
By Ming Gao,Hsiu-Ming (Sherman) Chang,Peter Lisherness,Kwang-Ting (Tim) Cheng
Issue Date:September 2011
pp. 1300-1312
There is a growing demand for online hardware checking capability to cope with increasing in-field failures resulting from variability and reliability problems. While many online checking schemes have been proposed, their area overhead remains too high for...
 
A case study of Time-Multiplexed Assertion Checking for post-silicon debugging
Found in: High-Level Design, Validation, and Test Workshop, IEEE International
By Ming Gao, Kwang-Ting (Tim) Cheng
Issue Date:June 2010
pp. 90-96
Post-silicon debugging has become the least predictable and most labor-intensive step in the modern design flow at 65nm and below. In this paper, we present a design-for-debug (DfD) technique — named Time-Multiplexed Assertion Checking (TMAC) — for post-si...
 
Digitally-Assisted Analog/RF Testing for Mixed-Signal SoCs
Found in: Asian Test Symposium
By Hsiu-Ming (Sherman) Chang, Min-Sheng (Mitchell) Lin, Kwang-Ting (Tim) Cheng
Issue Date:November 2008
pp. 43-48
We propose a testing methodology for analog and radio-frequency (RF) circuitry that incorporates digital circuits for performance calibration and adaptation. We explore the reuse of built-in digital calibration circuitry, along with minor digital design-fo...
 
Time-Multiplexed Online Checking: A Feasibility Study
Found in: Asian Test Symposium
By Ming Gao, Hsiu-Ming (Sherman) Chang, Peter Lisherness, Kwang-Ting (Tim) Cheng
Issue Date:November 2008
pp. 371-376
There is growing demand for online hardware checking capability to cope with increasing in-field failures resulting from variability and reliability problems. While many online checking schemes have been proposed, their area overhead remains too high for c...
 
Design and test for reliability and efficiency
Found in: IEEE Design and Test of Computers
By Tim Cheng
Issue Date:November 2008
pp. 508
This issue features two roundtables on electronic system-level (ESL) design, which has recently found its way into the mainstream EDA market. Composing system chips from basic building blocks is becoming increasingly more challenging as the number of devic...
 
Not just research as usual
Found in: IEEE Design and Test of Computers
By Tim Cheng
Issue Date:July 2008
pp. 292
This issue of IEEE Design & Test focuses on one of the five centers within the Focus Center Research Program (FCRP), the Gigascale Systems Research Center, which addresses systems architecture and design aspects of electronics systems in the late- and ...
 
Effective silicon debug is key for time to money
Found in: IEEE Design and Test of Computers
By Tim Cheng
Issue Date:May 2008
pp. 204
Effective silicon debug is key for time to money. Silicon debug and diagnosis attempt to locate and fix the root causes of failures upon identification of a chip that violates either a functional or timing specification. However, the tasks of silicon debug...
 
Bit-Error Rate Estimation for Bang-Bang Clock and Data Recovery Circuit in High-Speed Serial Links
Found in: VLSI Test Symposium, IEEE
By Dongwoo Hong, Kwang-Ting(Tim) Cheng
Issue Date:May 2008
pp. 17-22
Clock and data recovery (CDR) circuits incorporating a bang-bang (BB) phase detector have been widely adopted in high-speed serial links due to their advantages in high speed implementations. However, the heavily non-linear nature of the BB phase detector ...
 
Test compression saves bits, cycles, and money
Found in: IEEE Design and Test of Computers
By Tim Cheng
Issue Date:March 2008
pp. 105
Test data compression became an active research topic in the late 1990s, and has now become a standard offering within commercial DFT solutions. This issue of IEEE Design & Test features a special issue on the current state of test compression. This is...
 
From the EIC
Found in: IEEE Design and Test of Computers
By Tim Cheng
Issue Date:January 2008
pp. 4
The design of next-generation RFICs remains challenging and demands innovation. In addition, with signal frequencies reaching tens of GHz, testing these circuits has created extraordinary challenges. This issue of D&T features a special issue on design...
 
An Accurate Jitter Estimation Technique for Efficient High Speed I/O Testing
Found in: Asian Test Symposium
By Dongwoo Hong, Kwang-Ting (Tim) Cheng
Issue Date:October 2007
pp. 224-229
This paper describes a technique for estimating total jitter that, along with a loopback-based margining test, can be applied to test high speed serial interfaces. We first present the limitations of the existing estimation method, which is based on the du...
 
Trustworthy ICs for secure embedded computing
Found in: IEEE Design and Test of Computers
By Tim Cheng
Issue Date:November 2007
pp. 516
The design of secure and trusted embedded systems has recently drawn enormous attention from system-design practitioners. A secure system is only as strong as the weakest link. Therefore, any security functions implemented in an embedded system must be con...
 
Combining synchronous and asynchronous timing schemes for high-performance systems
Found in: IEEE Design and Test of Computers
By Tim Cheng
Issue Date:September 2007
pp. 412
Globally asynchronous, locally synchronous (GALS) design is emerging as the architecture of choice for certain applications. In a GALS system, the circuitry in each timing domain is locally synchronized, and different clock domains are glued together accor...
 
Design and CAD for Nanotechnologies
Found in: IEEE Design and Test of Computers
By Tim Cheng
Issue Date:July 2007
pp. 300
Recent innovations in nanoscale devices offer the potential for greater information density and system functionality. However, such devices present several new challenges. Design methodologies and tools have obtained a tremendous degree of sophistication a...
 
Supporting cost-effective innovation
Found in: IEEE Design and Test of Computers
By Tim Cheng
Issue Date:May 2007
pp. 212
In the nanoscale regime, speed and density of semiconductor technology continue to increase. However, skyrocketing design costs for developing gigascale system chips have slowed the creation of new design projects. Moreover, existing design and test soluti...
 
Cocktail approach to functional verification
Found in: IEEE Design and Test of Computers
By Tim Cheng
Issue Date:March 2007
pp. 108
Functional verification remains a major bottleneck of the design process. One approach to combating this bottleneck is to combine multiple, complementary techniques. This issue examines recent progress in this direction. The issue also includes two Perspec...
 
Moore's law meets the life sciences
Found in: IEEE Design and Test of Computers
By Tim Cheng
Issue Date:January 2007
pp. 4
The ability to perform DNA analysis, clinical diagnostics, and biomolecule detection and manipulation using miniaturized devices has many practical applications. This issue examines such devices, their functionality and applications, and the design and tes...
 
Handling variations and uncertainties
Found in: IEEE Design and Test of Computers
By Tim Cheng
Issue Date:November 2006
pp. 434
With increased technology scaling, high variability and low reliability will likely be the main challenges for chip design and testing. This issue discusses some of the key issues for handling increasing variations and uncertainties. Also, D&T's plans ...
 
The New World of ESL Design
Found in: IEEE Design and Test of Computers
By Kwang-Ting (Tim) Cheng
Issue Date:September 2006
pp. 333
This issue of IEEE Design & Test discusses some of the challenges of electronic system-level design and their corresponding solutions. In addition, a special section highlights the 2006 International Test Conference.
 
Vision from the Top
Found in: IEEE Design and Test of Computers
By Kwang-Ting (Tim) Cheng
Issue Date:July 2006
pp. 261
A popular DATE keynote speaker and an award-winning author are among the contributors to this issue, which covers on-chip testing, the sociology of EDA, quiescent-signal analysis, and a survey of test vector compression techniques.
 
The Need for a SiP Design and Test Infrastructure
Found in: IEEE Design and Test of Computers
By Kwang-Ting (Tim) Cheng
Issue Date:May 2006
pp. 181
Although successful and profitable applications have proven themselves in several market segments, significant challenges in system-in-package design and test remain for broader adoption.
 
Test Consideration for Nanometer-Scale CMOS Circuits
Found in: IEEE Design and Test of Computers
By Kaushik Roy, T.M. Mak, Kwang-Ting (Tim) Cheng
Issue Date:March 2006
pp. 128-136
Editor's note: Test technology faces new challenges as faults with increasingly complex behavior become predominant. Design approaches aimed at fixing some of the undesirable effects of nanometric technologies could jeopardize current test approaches. This...
 
Dealing with Early Life Failures
Found in: IEEE Design and Test of Computers
By Kwang-Ting (Tim) Cheng
Issue Date:March 2006
pp. 85
<em>D&T</em> editor in chief Tim Cheng discusses the industry's struggle to screen latent defects for complex ICs. He also welcomes two new editors to the <em>D&T</em> editorial board.
 
New beginnings, continued success
Found in: IEEE Design and Test of Computers
By Kwang-Ting (Tim) Cheng
Issue Date:January 2006
pp. 5-6
In his first EIC message as <em>D&T</em>'s new editor in chief, Tim Cheng notes that <em>D&T</em> has developed strong relationships with key electronic-design and test communities over the past several years. Such partnersh...
 
BER Estimation for Serial Links Based on Jitter Spectrum and Clock Recovery Characteristics
Found in: Test Conference, International
By Dongwoo Hong, Chee-Kian Ong, Kwang-Ting (Tim) Cheng
Issue Date:October 2004
pp. 1138-1147
High performance serial communication systems often require the Bit Error Rate (BER) to be at the level of 10-12 or below. The excessive test time for measuring such a low BER is a major hindrance in testing communication systems cost-effectively. In this ...
 
New Challenges in Delay Testing of Nanometer, Multigigahertz Designs
Found in: IEEE Design and Test of Computers
By T.M. Mak, Angela Krstic, Kwang-Ting (Tim) Cheng, Li-C. Wang
Issue Date:May 2004
pp. 241-247
Less predictable path delays and many paths with delays close to the clock period are the main trends affecting the delay testability of deep-submicron designs. This article examines the challenges in meeting the quality requirements of gigascale integrati...
 
A Scalable On-Chip Jitter Extraction Technique
Found in: VLSI Test Symposium, IEEE
By Chee-Kian Ong, Dongwoo Hong, Kwang-Ting (Tim) Cheng, Li-C Wang
Issue Date:April 2004
pp. 267
In this paper, we propose a method for extracting the spectral information of a multi-gigahertz jittery signal. This method utilizes existing on-chip single-shot period measurement techniques to sample and measure the period of multiple cycles of the multi...
 
Random Jitter Extraction Technique in a Multi-Gigahertz Signal
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Chee-Kian Ong, Dongwoo Hong, Kwang-Ting (Tim) Cheng, Li-C Wang
Issue Date:February 2004
pp. 10286
In this paper, we propose a simple technique for estimating the standard deviation of a Gaussian random jitter component in a multi-gigahertz signal. This method may utilize existing on-chip single-shot period measurement techniques to measure the multi-gi...
 
Jitter Spectral Extraction for Multi-Gigahertz Signal
Found in: Asia and South Pacific Design Automation Conference
By Chee-Kian Ong, Dongwoo Hong, Kwang-Ting (Tim) Cheng, Li-C Wang
Issue Date:January 2004
pp. 298-303
In this paper, we propose a method for extracting the spectral information of a multi-gigahertz jittery signal. This method may utilize existing on-chip single-shot period measurement techniques to measure the multi-gigahertz signal periods for spectral an...
 
A Signal Correlation Guided ATPG Solver And Its Applications For Solving Difficult Industrial Cases
Found in: Design Automation Conference
By Feng Lu, Li-C. Wang, K.-T. (Tim) Cheng, John Moondanos, Ziyad Hanna
Issue Date:June 2003
pp. 436
The developments of efficient SAT solvers have attracted tremendous research interest in recent years. The merits of these solvers are often compared in terms of their performance based upon a wide spread of benchmarks. In this paper, we extend an earlier-...
 
On Structural vs. Functional Testing for Delay Faults
Found in: Quality Electronic Design, International Symposium on
By Angela Krstic, Jing-Jia Liou, Kwang-Ting (Tim) Cheng, Li-C. Wang
Issue Date:March 2003
pp. 438
A structurally testable delay fault might become untestable in the functional mode of the circuit due to logic or timing constraints or both. Experimental data suggests that there could be a large difference in the number of structurally and functionally t...
 
Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems
Found in: Test Conference, International
By Ganapathy Parthasarathy, Madhu K. Iyer, Tao Feng, Li-C. Wang, Kwang-Ting (Tim) Cheng, Magdy S. Abadir
Issue Date:October 2002
pp. 203
In the past, Symbolic Trajectory Evaluation (STE) has been shown to be effective for verifying individual array blocks. However, when applying STE to verify multiple array blocks together as a single system, the run-time OBDD sizes would often blow up. In ...
 
Self-Referential Verification of Gate-Level Implementations of Arithmetic Circuits
Found in: Design Automation Conference
By Ying-Tsai Chang, Kwang-Ting (Tim) Cheng
Issue Date:June 2002
pp. 311
Verification of gate-level implementations of arithmetic circuits is challenging due to a number of reasons: the existence of some hard-to-verify arithmetic operators (e.g. multiplication), the use of different operand ordering, the incorporation of merged...
 
Self-Testing Second-Order Delta-Sigma Modulators Using Digital Stimulus
Found in: VLSI Test Symposium, IEEE
By Chee-Kian Ong, Kwang-Ting (Tim) Cheng
Issue Date:May 2002
pp. 0123
Single-bit second-order delta-sigma modulators are commonly used in high-resolution ADCs. Testing this type of modulator requires a high-resolution test stimulus, which is difficult to generate. This paper proposes a novel and robust technique to determine...
 
Induction-based Gate-level Verification of Multipliers
Found in: Computer-Aided Design, International Conference on
By Ying-Tsai Chang, Kwang-Ting (Tim) Cheng
Issue Date:November 2001
pp. 190
We propose a method based on unrolling the inductive definition of binary number multiplication to verify gate-level implementations of multipliers. The induction steps successively reduce the size of the multiplier under verification. Through induction, t...
 
Delay Testing Considering Crosstalk-Induced Effects
Found in: Test Conference, International
By Angela Krstic, Jing-Jia Liou, Yi-Min Jiang, Kwang-Ting (Tim) Cheng
Issue Date:November 2001
pp. 558
The increased noise/interference effects, such as crosstalk, power supply noise, substrate noise and distributed delay variations lead to increased signal integrity problems in deep submicron designs. These problems can cause logic errors and/or performanc...
 
HRM - A Hierarchical Simulator for Full-Chip Power Network Reliability Analysis
Found in: Quality Electronic Design, International Symposium on
By Yi-Min Jiang, Han Young Koh, Kwang-Ting (Tim) Cheng
Issue Date:March 2001
pp. 307
This paper presents a novel hierarchical simulation method for analyzing the power network reliability. Instead of performing full-chip simulation at the transistor level, this method first simulates each top-level block in the design individually to deriv...
 
Static Property Checking Using ATPG v.s. BDD Techniques
Found in: Test Conference, International
By Chung-Yang (Ric) Huang, Bwolen Yang, Huan-Chih Tsai, Kwang-Ting (Tim) Cheng
Issue Date:October 2000
pp. 309
Static property checking verifies pre-defined functional design rules such as
 
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