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Displaying 1-6 out of 6 total
Accelerating business analytics applications
Found in: High-Performance Computer Architecture, International Symposium on
By Valentina Salapura,Tejas Karkhanis,Priya Nagpurkar,Jose Moreira
Issue Date:February 2012
pp. 1-10
Business text analytics applications have seen rapid growth, driven by the mining of data for various decision making processes. Regular expression processing is an important component of these applications, consuming as much as 50% of their total executio...
 
A Top-Down Approach to Architecting CPI Component Performance Counters
Found in: IEEE Micro
By Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith
Issue Date:January 2007
pp. 84-93
Software developers can gain insight into software-hardware interactions by decomposing processor performance into individual cycles-per-instruction components that differentiate cycles consumed in active computation from those spent handling various miss ...
 
Energy Efficient Co-Adaptive Instruction Fetch and Issue
Found in: Computer Architecture, International Symposium on
By Alper Buyuktosunoglu, Tejas Karkhanis, David H. Albonesi, Pradip Bose
Issue Date:June 2003
pp. 147
Front-end instruction delivery accounts for a significant fraction of the energy consumed in a dynamic superscalar processor. The issue queue in these processors serves two crucial roles: it bridges the front and back ends of the processor and serves as th...
 
A mechanistic performance model for superscalar out-of-order processors
Found in: ACM Transactions on Computer Systems (TOCS)
By James E. Smith, Lieven Eeckhout, Stijn Eyerman, Tejas Karkhanis
Issue Date:May 2009
pp. 1-37
A mechanistic model for out-of-order superscalar processors is developed and then applied to the study of microarchitecture resource scaling. The model divides execution time into intervals separated by disruptive miss events such as branch mispredictions ...
     
A performance counter architecture for computing accurate CPI components
Found in: Proceedings of the 12th international conference on Architectural support for programming languages and operating systems (ASPLOS-XII)
By James E. Smith, Lieven Eeckhout, Stijn Eyerman, Tejas Karkhanis
Issue Date:October 2006
pp. 109-es
A common way of representing processor performance is to use Cycles per Instruction (CPI) `stacks' which break performance into a baseline CPI plus a number of individual miss event CPI components. CPI stacks can be very helpful in gaining insight into the...
     
Saving energy with just in time instruction delivery
Found in: Proceedings of the 2002 international symposium on Low power electronics and design (ISLPED '02)
By James E. Smith, Pradip Bose, Tejas Karkhanis
Issue Date:August 2002
pp. 178-183
Just-In-Time instruction delivery is a general method for saving energy in a microprocessor by dynamically limiting the number of in-flight instructions. The goal is to save energy by 1) fetching valid instructions no sooner than necessary, avoiding cycles...
     
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