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Displaying 1-30 out of 30 total
Fault Injection Resilience
Found in: Fault Diagnosis and Tolerance in Cryptography, Workshop on
By Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane
Issue Date:August 2010
pp. 51-65
Fault injections constitute a major threat to the security of embedded systems. Errors occurring in the cryptographic algorithms have been shown to be extremely dangerous, since powerful attacks can exploit few of them to recover the full secrets. Most of ...
 
Security evaluation of different AES implementations against practical setup time violation attacks in FPGAs
Found in: Hardware-Oriented Security and Trust, IEEE International Workshop on
By Shivam Bhasin, Nidhal Selmane, Sylvain Guilley, Jean-Luc Danger
Issue Date:July 2009
pp. 15-21
Security evaluation of various AES implementation against practical power attacks has been reported in literature. However, to the authors' knowledge, very few of the fault attacks reported on AES have been practically realized. Since sbox is a crucial ele...
 
Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors
Found in: IEEE Design and Test of Computers
By Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Renaud Pacalet, Yves Mathieu
Issue Date:November 2007
pp. 546-555
This article presents a comprehensive back-end design flow that enables the realization of constant-power cryptoprocessors, natively protected against side-channel attacks exploiting the instant power consumption. The proposed methodology is based on a ful...
 
Hardware Trojan Horses in Cryptographic IP Cores
Found in: 2013 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC)
By Shivam Bhasin,Jean-Luc Danger,Sylvain Guilley,Xuan Thuy Ngo,Laurent Sauvage
Issue Date:August 2013
pp. 15-29
Detecting hardware trojans is a difficult task in general. In this article we study hardware trojan horses insertion and detection in cryptographic intellectual property (IP) blocks. The context is that of a fabless design house that sells IP blocks as GDS...
 
From Cryptography to Hardware: Analyzing Embedded Xilinx BRAM for Cryptographic Applications
Found in: 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture Workshops (MICROW)
By Shivam Bhasin,Sylvain Guilley,Jean-Luc Danger
Issue Date:December 2012
pp. 1-8
Design of cryptographic applications need special care. For instance, physical attacks like Side-Channel Analysis (SCA) are able to recover the secret key, just by observing the activity of the computation, even for mathematically robust algorithms like AE...
 
Wavelet transform based pre-processing for side channel analysis
Found in: 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture Workshops (MICROW)
By Nicolas Debande,Youssef Souissi,M. Abdelaziz El Aabid,Sylvain Guilley,Jean-Luc Danger
Issue Date:December 2012
pp. 32-38
We suggest, in a methodological manner, the use of Wavelet transforms to improve side channel analysis (SCA). The proposed applications are involved in several side channel analysis aspects: storage of traces, patterns detection and noise filtering. We sho...
 
Random Active Shield
Found in: 2012 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC)
By Sebastien Briais,Jean-Michel Cioranesco,Jean-Luc Danger,Sylvain Guilley,David Naccache,Thibault Porteboeuf
Issue Date:September 2012
pp. 103-113
Recently, some active shielding techniques have been broken (e.g. by FlyLogic). The caveat is that their geometry is easy to guess, and thus they can be bypassed with an affordable price. This paper has two contributions. First of all, it provides a defini...
 
Efficient Dual-Rail Implementations in FPGA Using Block RAMs
Found in: Reconfigurable Computing and FPGAs, International Conference on
By Shivam Bhasin,Sylvain Guilley,Youssef Souissi,Tarik Graba,Jean-Luc Danger
Issue Date:December 2011
pp. 261-267
Dual-rail precharge logic (DPL) are hardware countermeasures deployed to protect cryptographic coprocessors. However, their implementation on FPGA has been an issue of concern mainly due to imbalanced routing and early propagation effect. We analyzed the c...
 
Cross-Correlation Cartography
Found in: Information Forensics and Security, IEEE International Workshop on
By Nicolas Debande,Youssef Souissi,Maxime Nassar,Sylvain Guilley, Thanh-Ha Le,Jean-Luc Danger
Issue Date:December 2011
pp. 1-6
Modern embedded systems rely on cryptographic co-processor to ensure security. These cryptographic co-processor are theoretically secure but their physical implementations are vulnerable against Side-Channel Analysis (SCA). Therefore, embedded systems shou...
 
Cross-Correlation Cartography
Found in: Reconfigurable Computing and FPGAs, International Conference on
By Laurent Sauvage, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu
Issue Date:December 2010
pp. 268-273
Side channel and fault injection attacks are a major threat to cryptographic applications of embedded systems. Best performances for these attacks are achieved by focusing sensors or injectors on the sensible parts of the application, by means of dedicated...
 
Evaluation of White-Box and Grey-Box Noekeon Implementations in FPGA
Found in: Reconfigurable Computing and FPGAs, International Conference on
By Zouha Cherif, Florent Flament, Jean-Luc Danger, Shivam Bhasin, Sylvain Guilley, Hervé Chabanne
Issue Date:December 2010
pp. 310-315
White-box implementations of cryptographic algorithms aim to denying the key readout even if the source code embedding the key is disclosed. They are based on sets of large tables perfectly known by the user but including unknown encoding functions. While ...
 
Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics
Found in: IEEE Transactions on Computers
By Sylvain Guilley, Laurent Sauvage, Florent Flament, Vinh-Nga Vong, Philippe Hoogvorst, Renaud Pacalet
Issue Date:September 2010
pp. 1250-1263
Cryptographic circuits are nowadays subject to attacks that no longer focus on the algorithm but rather on its physical implementation. Attacks exploiting information leaked by the hardware implementation are called side-channel attacks (SCAs). Among these...
 
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow
Found in: Reconfigurable Computing and FPGAs, International Conference on
By Shivam Bhasin, Jean-Luc Danger, Florent Flament, Tarik Graba, Sylvain Guilley, Yves Mathieu, Maxime Nassar, Laurent Sauvage, Nidhal Selmane
Issue Date:December 2009
pp. 213-218
The main challenge when implementing cryptographic algorithms in hardware is to protect them against attacks that target directly the device. Two strategies are customarily employed by malevolent adversaries: observation and differential perturbation attac...
 
DPL on Stratix II FPGA: What to Expect?
Found in: Reconfigurable Computing and FPGAs, International Conference on
By Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu
Issue Date:December 2009
pp. 243-248
FPGA design of side channel analysis countermeasure using unmasked dual-rail with precharge logic appears to be a great challenge. Indeed, the robustness of such a solution relies on careful differential placement and routing, whereas both FPGA layout and ...
 
WDDL is Protected against Setup Time Violation Attacks
Found in: Fault Diagnosis and Tolerance in Cryptography, Workshop on
By Nidhal Selmane, Shivam Bhasin, Sylvain Guilley, Tarik Graba, Jean-Luc Danger
Issue Date:September 2009
pp. 73-83
In order to protect crypto-systems against side channel attacks various countermeasures have been implemented such as dual-rail logic or masking. Faults attacks are a powerful tool to break some implementations of robust cryptographic algorithms such as AE...
 
Deconvolving Protected Signals
Found in: Availability, Reliability and Security, International Conference on
By Mohaned Kafi, Sylvain Guilley, Sandra Marcello, David Naccache
Issue Date:March 2009
pp. 687-694
The variable clock (VC) side-channel countermeasure consists in clocking a chip with an internal oscillator whose parameters (frequency, duty cycle, shape, etc.) vary randomly in time. In this paper, we use parametric deconvolution to process VC-power cons...
 
Silicon-level Solutions to Counteract Passive and Active Attacks
Found in: Fault Diagnosis and Tolerance in Cryptography, Workshop on
By Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane, Renaud Pacalet
Issue Date:August 2008
pp. 3-17
This article presents a family of cryptographic ASICs, called SecMat, designed in CMOS 130 nanometer technology by the authors with the help of STMicroelectronics.The purpose of these prototype circuits is to experience with the published ``implementation-...
 
Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks
Found in: IEEE Transactions on Computers
By Sylvain Guilley, Laurent Sauvage, Philippe Hoogvorst, Renaud Pacalet, Guido Marco Bertoni, Sumanta Chaudhuri
Issue Date:November 2008
pp. 1482-1497
Power-constant logic styles are promising solutions to counter-act side-channel attacks on sensitive cryptographic devices. Recently, one vulnerability has been identified in a standard-cell based power-constant logic called WDDL. Another logic, nicknamed ...
 
Place-and-route impact on the security of DPL designs in FPGAs
Found in: Hardware-Oriented Security and Trust, IEEE International Workshop on
By Sylvain Guilley, Sumanta Chaudhuri, Laurent Sauvage, Tarik Graba, Jean-Luc Danger, Philippe Hoogvorst, Vinh-Nga Vong, Maxime Nassar
Issue Date:June 2008
pp. 26-32
Straightforward implementations of cryptographic algorithms are known to be vulnerable to attacks aimed not at the mathematical structure of the cipher but rather at the weak points of the electronic devices which implement it. These attacks, known as side...
 
Practical Setup Time Violation Attacks on AES
Found in: Seventh European Dependable Computing Conference
By Nidhal Selmane, Sylvain Guilley, Jean-Luc Danger
Issue Date:May 2008
pp. 91-96
Faults attacks are a powerful tool to break some implementations of robust cryptographic algorithms such as AES and DES . Various methods of faults attackon cryptographic systems have been discovered and researched[1]. However, to the authors’ knowledge, a...
 
CMOS Structures Suitable for Secured Hardware
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet, Jean Provost
Issue Date:February 2004
pp. 21414
Unsecured electronic circuits leak physical syndromes correlated to the data they handle. Side-channels attacks, like SPA or DPA, exploit this information leakage. We provide balanced and memoryless CMOS structures for a 2-input secured NAND gate.
   
Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs
Found in: Secure System Integration and Reliability Improvement
By Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Tarik Graba, Yves Mathieu
Issue Date:July 2008
pp. 16-23
FPGAs are often considered for high-end applications that require embedded cryptography. These devices must thus be protected against physical attacks. However, unlike ASICs, in which custom and backend-level counter-measures can be devised, FPGAs offer le...
 
Hardware-enforced Protection against Software Reverse-Engineering based on an Instruction Set Encoding
Found in: Proceedings of ACM SIGPLAN on Program Protection and Reverse Engineering Workshop 2014 (PPREW'14)
By Florian Praden, Jean-Luc Danger, Sylvain Guilley
Issue Date:January 2014
pp. 1-11
Software programs are prone to reverse-engineering. Protection usually consists either in obfuscation or Randomized Instruction Set Emulation (RISE). In this article, we explore a mixed software/hardware RISE suitable for embedded systems. This solution is...
     
Formal Analysis of CRT-RSA Vigilant's Countermeasure Against the BellCoRe Attack: A Pledge for Formal Methods in the Field of Implementation Security
Found in: Proceedings of ACM SIGPLAN on Program Protection and Reverse Engineering Workshop 2014 (PPREW'14)
By Pablo Rauzy, Sylvain Guilley
Issue Date:January 2014
pp. 1-10
In our paper at PROOFS 2013, we formally studied a few known countermeasures to protect CRT-RSA against the BellCoRe fault injection attack. However, we left Vigilant's countermeasure and its alleged repaired version by Coron et al. as future work, because...
     
High-order timing attacks
Found in: Proceedings of the First Workshop on Cryptography and Security in Computing Systems (CS2 '14)
By Jean-Luc Danger, Nicolas Debande, Sylvain Guilley, Youssef Souissi
Issue Date:January 2014
pp. 7-12
The timing attack (TA) is a side-channel analysis (SCA) variant that exploits information leakage through the computation duration. Previously, leakages in timing have been exploited by comparison analysis, most often thanks to "correlation - collision" or...
     
Side-channel indistinguishability
Found in: Proceedings of the 2nd International Workshop on Hardware and Architectural Support for Security and Privacy (HASP '13)
By Claude Carlet, Sylvain Guilley
Issue Date:June 2013
pp. 1-8
We introduce a masking strategy for hardware that prevents any side-channel attacker from recovering uniquely the secret key of a cryptographic device. In this masking scheme, termed homomorphic, the sensitive data is exclusive-ored with a random value tha...
     
Countering early evaluation: an approach towards robust dual-rail precharge logic
Found in: Proceedings of the 5th Workshop on Embedded Systems Security (WESS '10)
By Florent Flament, Jean-Luc Danger, Nidhal Selmane, Shivam Bhasin, Sylvain Guilley
Issue Date:October 2010
pp. 1-8
Wave Dynamic Differential Logic (WDDL) is a hiding countermeasure to thrawt side channel attacks (SCA). It suffers from a vulnerability called Early Evaluation, i.e. calculating output before all inputs are valid. This causes delay biases in WDDL even when...
     
An 8x8 run-time reconfigurable FPGA embedded in a SoC
Found in: Proceedings of the 45th annual conference on Design automation (DAC '08)
By Florent Flament, Jean-Luc Danger, Philippe Hoogvorst, Sumanta Chaudhuri, Sylvain Guilley
Issue Date:June 2008
pp. 1-30
This paper presents a RTR FPGA embedded in a System on Chip fabricated in 130nm CMOS process. Various aspects of the design flow, from automation to floor-planning are discussed. We explain the measures taken in the FPGA design to guarantee RTR functionali...
     
Efficient tiling patterns for reconfigurable gate arrays
Found in: Proceedings of the 2008 international workshop on System level interconnect prediction (SLIP '08)
By Jean-Luc Danger, Philippe Hoogvorst, Sumanta Chaudhuri, Sylvain Guilley
Issue Date:April 2008
pp. 24-31
In this paper we present a few potentially efficient tiling patterns for gate-array realizations. We start with a brief recapitulation of tiling patterns, and fundamental limits of placement/routing in a two-dimensional plane. We state the first principles...
     
Efficient tiling patterns for reconfigurable gate arrays
Found in: Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays (FPGA '08)
By Jean-Luc Danger, Philippe Hoogvorst, Sumanta Chaudhuri, Sylvain Guilley
Issue Date:February 2008
pp. 1-89
This article does a purely mathematical analysis based on generic models, and the idea is to investigate the possibility of using tiling patterns other than Manhattan grid in FPGAs. The goal of our research is to evolve FPGA architectures with advances in ...
     
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