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Reliable Computing with Ultra-Reduced Instruction Set Co-processors
Found in: IEEE Micro
By Dan Wang,Aravindkumar Rajendiran,Hiren Patel,Sundaram Ananthanarayanan,Mahesh Tripunitara,Siddharth Garg
Issue Date:December 2013
pp. 1
This work presents a method to reliably perform computations in the presence of hard faults arising from aggressive technology scaling, and design defects from human error. Our method is based on the observation that a single Turing-complete instruction ca...
 
EmPower: FPGA based emulation of dynamic power management algorithms for multi-core systems on chip (abstract only)
Found in: Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays (FPGA '12)
By Andrew Kennings, Chirag Ravishankar, Sundaram Ananthanarayanan, Siddharth Garg
Issue Date:February 2012
pp. 266-266
Dynamic power management for multi-core system on chip (MPSoC) platforms has become an increasingly critical design problem. In this paper, we present EmPower, an FPGA based emulation, validation and prototyping framework for dynamic power management resea...
     
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