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Displaying 1-32 out of 32 total
Systems Directions for Pervasive Computing
Found in: Hot Topics in Operating Systems, Workshop on
By Robert Grimm, Janet Davis, Ben Hendrickson, Eric Lemar, Adam MacBeth, Steven Swanson, Tom Anderson, Brian Bershad, Gaetano Borriello, Steven Gribble, David Wetherall
Issue Date:May 2001
pp. 0147
Abstract: Pervasive computing, with its focus on users and their tasks rather than on computing devices and technology, provides an attractive vision for the future of computing. But, while hardware and networking infrastructure to realize this vision are ...
 
Dark Silicon [Guest editors' introduction]
Found in: IEEE Micro
By Michael B. Taylor,Steven Swanson
Issue Date:September 2013
pp. 6-7
This introduction to the special issue discusses"dark silicon"--chip area that must remain unclocked or underclocked--and highlights the five articles in the issue.
   
Dark Silicon [Guest editors' introduction]
Found in: IEEE Micro
By Michael B. Taylor,Steven Swanson
Issue Date:September 2013
pp. 6-7
This introduction to the special issue discusses"dark silicon"--chip area that must remain unclocked or underclocked--and highlights the five articles in the issue.
   
Rethinking Flash in the Data Center
Found in: IEEE Micro
By David G. Andersen, Steven Swanson
Issue Date:July 2010
pp. 52-54
<p>Deployment of flash memory depends on making the most of its unique properties instead of treating it as a drop-in replacement for existing technologies.</p>
 
Gordon: An Improved Architecture for Data-Intensive Applications
Found in: IEEE Micro
By Adrian M. Caulfield, Laura M. Grupp, Steven Swanson
Issue Date:January 2010
pp. 121-130
<p>Gordon is a system architecture for data-centric applications combining low-power processors, flash memory, and data-centric programming systems to improve performance and efficiency for data-centric applications. The article explores the Gordon d...
 
The WaveScalar architecture
Found in: ACM Transactions on Computer Systems (TOCS)
By Andrew Petersen, Andrew Putnam, Andrew Schwerin, Ken Michelson, Mark Oskin, Martha Mercaldi, Steven Swanson, Susan J. Eggers, Andrew Petersen, Andrew Putnam, Andrew Schwerin, Ken Michelson, Mark Oskin, Martha Mercaldi, Steven Swanson, Susan J. Eggers
Issue Date:May 2007
pp. 1-54
Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, however, is an open challenge that conventional superscalar designs will not be ...
     
Refactor, Reduce, Recycle: Restructuring the I/O Stack for the Future of Storage
Found in: Computer
By Steven Swanson,Adrian M. Caulfield
Issue Date:August 2013
pp. 52-59
Emerging nonvolatile storage technologies promise orders-of-magnitude bandwidth increases and latency reductions, but fully realizing their potential requires minimizing storage software overhead and rethinking the roles of hardware and software in storage...
 
Latency-Optimized Networks for Clustering FPGAs
Found in: 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
By Trevor Bunker,Steven Swanson
Issue Date:April 2013
pp. 129-136
The data-intensive applications that will shape computing in the coming decades require scalable architectures that incorporate scalable data and compute resources and can support random requests to unstructured (e.g., logs) and semi-structured (e.g., larg...
 
Minerva: Accelerating Data Analysis in Next-Generation SSDs
Found in: 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
By Arup De,Maya Gokhale,Rajesh Gupta,Steven Swanson
Issue Date:April 2013
pp. 9-16
Emerging non-volatile memory (NVM) technologies have DRAM-like latency with storage-like density, offering unique capability to analyze large data sets significantly faster than flash or disk storage. However, the hybrid nature of these NVM technologies su...
 
Underclocked Software Prefetching: More Cores, Less Energy
Found in: IEEE Micro
By Md Kamruzzaman,Steven Swanson,Dean M. Tullsen
Issue Date:July 2012
pp. 32-41
Power consumption is a concern for helper-thread prefetching that uses extra cores to speed up the single-thread execution, because power consumption increases with each additional core. This article analyzes the impact of using power-saving techniques in ...
 
An Evaluation of Selective Depipelining for FPGA-Based Energy-Reducing Irregular Code Coprocessors
Found in: International Conference on Field Programmable Logic and Applications
By Jack Sampson,Manish Arora,Nathan Goulding-Hotta,Ganesh Venkatesh,Jonathan Babb,Vikram Bhatt,Steven Swanson,Michael Bedford Taylor
Issue Date:September 2011
pp. 24-29
As the complexity of FPGA-based systems scales, the importance of efficiently handling irregular code increases. Recent work has proposed Irregular Code Energy Reducers (ICERs), a high-level synthesis approach for FPGAs that offers significant energy reduc...
 
Reducing the Energy Cost of Irregular Code Bases in Soft Processor Systems
Found in: Field-Programmable Custom Computing Machines, Annual IEEE Symposium on
By Manish Arora, Jack Sampson, Nathan Goulding-Hotta, Jonathan Babb, Ganesh Venkatesh, Michael Bedford Taylor, Steven Swanson
Issue Date:May 2011
pp. 210-213
This paper describes an architecture and FPGA synthesis tool chain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide range of unmodified C programs. FPGAs are increasingly used to build large-scal...
 
Efficient complex operators for irregular codes
Found in: High-Performance Computer Architecture, International Symposium on
By Jack Sampson, Ganesh Venkatesh, Nathan Goulding-Hotta, Saturnino Garcia, Steven Swanson, Michael Bedford Taylor
Issue Date:February 2011
pp. 491-502
Complex
 
Moneta: A High-Performance Storage Array Architecture for Next-Generation, Non-volatile Memories
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Adrian M. Caulfield, Arup De, Joel Coburn, Todor I. Mollow, Rajesh K. Gupta, Steven Swanson
Issue Date:December 2010
pp. 385-395
Emerging non-volatile memory technologies such as phase change memory (PCM) promise to increase storage system performance by a wide margin relative to both conventional disks and flash-based SSDs. Realizing this potential will require significant changes ...
 
Area-Performance Trade-offs in Tiled Dataflow Architectures
Found in: Computer Architecture, International Symposium on
By Steven Swanson, Andrew Putnam, Martha Mercaldi, Martha Mercaldi, Ken Michelson, Andrew Petersen, Andrew Schwerin, Mark Oskin, Susan J. Eggers
Issue Date:June 2006
pp. 314-326
Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and performance. The basic premise of these architectures is that larger, higher-per...
 
WaveScalar
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Steven Swanson, Ken Michelson, Andrew Schwerin, Mark Oskin
Issue Date:December 2003
pp. 291
Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, however, is an open challenge. Ever increasing wire-delay relative to switching ...
 
Understanding the Impact of Emerging Non-Volatile Memories on High-Performance, IO-Intensive Computing
Found in: SC Conference
By Adrian M. Caulfield, Joel Coburn, Todor Mollov, Arup De, Ameen Akel, Jiahua He, Arun Jagatheesan, Rajesh K. Gupta, Allan Snavely, Steven Swanson
Issue Date:November 2010
pp. 1-11
Emerging storage technologies such as flash memories, phase-change memories, and spin-transfer torque memories are poised to close the enormous performance gap between disk-based storage and main memory. We evaluate several approaches to integrating these ...
 
Near-Data Processing: Insights from a MICRO-46 Workshop
Found in: IEEE Micro
By Rajeev Balasubramonian,Jichuan Chang,Troy Manning,Jaime H. Moreno,Richard Murphy,Ravi Nair,Steven Swanson
Issue Date:July 2014
pp. 36-42
The cost of data movement in big-data systems motivates careful examination of near-data processing (NDP) frameworks. The concept of NDP was actively researched in the 1990s, but gained little commercial traction. After a decade-long dormancy, interest in ...
 
System support for pervasive applications
Found in: ACM Transactions on Computer Systems (TOCS)
By Adam Macbeth, Brian Bershad, David Wetherall, Eric Lemar, Gaetano Borriello, Janet Davis, Robert Grimm, Steven Gribble, Steven Swanson, Thomas Anderson
Issue Date:November 2004
pp. 421-486
Pervasive computing provides an attractive vision for the future of computing. Computational power will be available everywhere. Mobile and stationary devices will dynamically connect and coordinate to seamlessly help people in accomplishing their tasks. F...
     
Bankshot: caching slow storage in fast non-volatile memory
Found in: Proceedings of the 1st Workshop on Interactions of NVM/FLASH with Operating Systems and Workloads (INFLOW '13)
By Jian Xu, Meenakshi Sundaram Bhaskaran, Steven Swanson
Issue Date:November 2013
pp. 1-9
Emerging non-volatile storage (e.g., Phase Change Memory, STT-RAM) allow access to persistent data at latencies an order of magnitude lower than SSDs. The density and price gap between NVMs and denser storage make NVM economically most suitable as a cache ...
     
Load-balanced pipeline parallelism
Found in: Proceedings of SC13: International Conference for High Performance Computing, Networking, Storage and Analysis (SC '13)
By Md Kamruzzaman, Steven Swanson, Dean M. Tullsen
Issue Date:November 2013
pp. 1-12
Accelerating a single thread in current parallel systems remains a challenging problem, because sequential threads do not naturally take advantage of the additional cores. Recent work shows that automatic extraction of pipeline parallelism is an effective ...
     
From ARIES to MARS: transaction support for next-generation, solid-state drives
Found in: Proceedings of the Twenty-Fourth ACM Symposium on Operating Systems Principles (SOSP '13)
By Joel Coburn, Meir Schwarz, Rajesh Gupta, Steven Swanson, Trevor Bunker
Issue Date:November 2013
pp. 197-212
Transaction-based systems often rely on write-ahead logging (WAL) algorithms designed to maximize performance on disk-based storage. However, emerging fast, byte-addressable, non-volatile memory (NVM) technologies (e.g., phase-change memories, spin-transfe...
     
QuickSAN: a storage area network for fast, distributed, solid state disks
Found in: Proceedings of the 40th Annual International Symposium on Computer Architecture (ISCA '13)
By Adrian M. Caulfield, Steven Swanson
Issue Date:June 2013
pp. 464-474
Solid State Disks (SSDs) based on flash and other non-volatile memory technologies reduce storage latencies from 10s of milliseconds to 10s or 100s of microseconds, transforming previously inconsequential storage overheads into performance bottlenecks. Thi...
     
Underpowering NAND flash: profits and perils
Found in: Proceedings of the 50th Annual Design Automation Conference (DAC '13)
By Hung-Wei Tseng, Steven Swanson
Issue Date:May 2013
pp. 1-6
MLC Flash memory is getting more popular in computer systems ranging from sensor networks and embedded systems to large-scale server systems. However, MLC flash has many reliability concerns, including the potential for corruption due to supply voltage flu...
     
Coalition threading: combining traditional andnon-traditional parallelism to maximize scalability
Found in: Proceedings of the 21st international conference on Parallel architectures and compilation techniques (PACT '12)
By Dean M. Tullsen, Md Kamruzzaman, Steven Swanson
Issue Date:September 2012
pp. 273-282
Non-traditional parallelism provides parallel speedup for a single thread without the need to manually divide and coordinate computation. This paper describes coalition threading, a technique that seeks the ideal combination of traditional and non-traditio...
     
Providing safe, user space access to fast, solid state disks
Found in: Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '12)
By Adrian M. Caulfield, Joel Coburn, Steven Swanson, Todor I. Mollov, Arup De, Louis Alex Eisner
Issue Date:March 2012
pp. 387-400
Emerging fast, non-volatile memories (e.g., phase change memories, spin-torque MRAMs, and the memristor) reduce storage access latencies by an order of magnitude compared to state-of-the-art flash-based SSDs. This improved performance means that software o...
     
QsCores: trading dark silicon for scalable energy efficiency with quasi-specific cores
Found in: Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-44 '11)
By Michael Bedford Taylor, Nathan Goulding-Hotta, Sravanthi Kota Venkata, Steven Swanson, Ganesh Venkatesh, Jack Sampson
Issue Date:December 2011
pp. 163-174
Transistor density continues to increase exponentially, but power dissipation per transistor is improving only slightly with each generation of Moore's law. Given the constant chip-level power budgets, this exponentially decreases the percentage of transis...
     
Conservation cores: reducing the energy of mature computations
Found in: Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems (ASPLOS '10)
By Ganesh Venkatesh, Jack Sampson, Jose Lugo-Martinez, Michael Bedford Taylor, Nathan Goulding, Saturnino Garcia, Steven Swanson, Vladyslav Bryksin
Issue Date:March 2010
pp. 222-230
Growing transistor counts, limited power budgets, and the breakdown of voltage scaling are currently conspiring to create a utilization wall that limits the fraction of a chip that can run at full speed at one time. In this regime, specialized, energy-effi...
     
Characterizing flash memory: anomalies, observations, and applications
Found in: Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (Micro-42)
By Adrian M. Caulfield, Eitan Yaakobi, Jack K. Wolf, Joel Coburn, Laura M. Grupp, Paul H. Siegel, Steven Swanson
Issue Date:December 2009
pp. 24-33
Despite flash memory's promise, it suffers from many idiosyncrasies such as limited durability, data integrity problems, and asymmetry in operation granularity. As architects, we aim to find ways to overcome these idiosyncrasies while exploiting flash memo...
     
Gordon: using flash memory to build fast, power-efficient clusters for data-intensive applications
Found in: Proceeding of the 14th international conference on Architectural support for programming languages and operating systems (ASPLOS '09)
By Adrian M. Caulfield, Laura M. Grupp, Steven Swanson
Issue Date:March 2009
pp. 23-27
As our society becomes more information-driven, we have begun to amass data at an astounding and accelerating rate. At the same time, power concerns have made it difficult to bring the necessary processing power to bear on querying, processing, and underst...
     
Instruction scheduling for a tiled dataflow architecture
Found in: Proceedings of the 12th international conference on Architectural support for programming languages and operating systems (ASPLOS-XII)
By Andrew Petersen, Andrew Putnam, Andrew Schwerin, Mark Oskin, Martha Mercaldi, Steven Swanson, Susan J. Eggers
Issue Date:October 2006
pp. 109-es
This paper explores hierarchical instruction scheduling for a tiled processor. Our results show that at the top level of the hierarchy, a simple profile-driven algorithm effectively minimizes operand latency. After this schedule has been partitioned into l...
     
Modeling instruction placement on a spatial architecture
Found in: Proceedings of the eighteenth annual ACM symposium on Parallelism in algorithms and architectures (SPAA '06)
By Andrew Petersen, Andrew Putnam, Andrew Schwerin, Mark Oskin, Martha Mercaldi, Steven Swanson, Susan J. Eggers
Issue Date:July 2006
pp. 158-169
In response to current technology scaling trends, architects are developing a new style of processor, known as spatial computers. A spatial computer is composed of hundreds or even thousands of simple, replicated processing elements (or PEs), frequently or...
     
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