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Displaying 1-6 out of 6 total
Power Management in the Amulet Microprocessors
Found in: IEEE Design and Test of Computers
By Steve B. Furber, Aristides Efthymiou, Jim D. Garside, David W. Lloyd, Mike J.G. Lewis, Steve Temple
Issue Date:March 2001
pp. 42-52
Amulet microprocessors are asynchronous (clockless) implementations of the ARM 32-bit RISC architecture. Their asynchronous control framework has positive benefits for low-power applications because it reduces activity to the minimum required to perform a ...
Overview of the SpiNNaker System Architecture
Found in: IEEE Transactions on Computers
By Steve B. Furber,David R. Lester,Luis A. Plana,Jim D. Garside,Eustace Painkras,Steve Temple,Andrew D. Brown
Issue Date:December 2013
pp. 2454-2467
SpiNNaker (a contraction of Spiking Neural Network Architecture) is a million-core computing engine whose flagship goal is to be able to simulate the behavior of aggregates of up to a billion neurons in real time. It consists of an array of ARM9 cores, com...
Modeling Spiking Neural Networks on SpiNNaker
Found in: Computing in Science and Engineering
By Xin Jin, Mikel Luján, Luis A. Plana, Sergio Davies, Steve Temple, Steve B. Furber
Issue Date:September 2010
pp. 91-97
<p>SpiNNaker is a massively parallel architecture with more than a million processing cores that can model up to 1 billion spiking neurons in biological real time.</p>
A GALS Infrastructure for a Massively Parallel Multiprocessor
Found in: IEEE Design and Test of Computers
By Luis A. Plana, Steve B. Furber, Steve Temple, Mukaram Khan, Yebin Shi, Jian Wu, Shufan Yang
Issue Date:September 2007
pp. 454-463
The Spinnaker (Spiking Neural Network Architecture) system for large-scale neural modeling is based on a scalable processor chip containing multiple ARM cores. Using a globally asynchronous, locally synchronous (GALS) approach allows custom, off-the-shelf ...
SpiNNaker - programming model
Found in: IEEE Transactions on Computers
By Andrew Brown,Steve Furber,Jeffrey Reeve,Jim Garside,Kier Dugan,Luis Plana,Steve Temple
Issue Date:June 2014
pp. 1
SpiNNaker is a multi-core computing engine, with a bespoke and specialised communication infrastructure that supports almost perfect scalability up to a hard limit of 216x18=1179648 cores. This remarkable property is achieved at the cost of ignoring memory...
SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip
Found in: ACM Journal on Emerging Technologies in Computing Systems (JETC)
By David Clark, Eustace Painkras, Jeffrey Pepper, Jim Garside, John Bainbridge, Luis A. Plana, Simon Davidson, Steve Furber, Steve Temple
Issue Date:December 2011
pp. 1-18
The design and implementation of globally asynchronous locally synchronous systems-on-chip is a challenging activity. The large size and complexity of the systems require the use of computer-aided design (CAD) tools but, unfortunately, most tools do not wo...