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Guest Editors' Introduction: Promises and Challenges of Novel Interconnect Technologies
IEEE Design and Test of Computers
By Partha Pratim Pande, Sriram Vangal
Issue Date:July 2010
<p>This special issue highlights recent investigations of various revolutionary interconnect paradigms as to whether they can deliver on the promise of greater integration, high performance, good scalability, and high energy efficiency in future SoCs...
A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip
VLSI Design, International Conference on
By Praveen Salihundam,Mohammed Asadullah Khan,Shailendra Jain,Yatin Hoskote,Satish Yada,Shasi Kumar,Vasantha Erraguntla,Sriram Vangal,Nitin Borkar
Issue Date:January 2012
A reconfigurable on-die Traffic Generator (TG) is proposed to test the packet switched 2D-mesh network of a 48 iA-32 core Single-chip Cloud Computer. The Single-chip Cloud Computer (SCC) is an experimental processor created by Intel Labs. The 24-tile Netwo...
A 5-GHz Mesh Interconnect for a Teraflops Processor
By Yatin Hoskote, Sriram Vangal, Arvind Singh, Nitin Borkar, Shekhar Borkar
Issue Date:September 2007
A multicore processor in 65-nm technology with 80 single-precision, floating-point cores delivers performance in excess of a teraflops while consuming less than 100 W. A 2D on-die mesh interconnection network operating at 5 GHz provides the high-performanc...
The 48-core SCC Processor: the Programmer's View
By Timothy G. Mattson, Michael Riepen, Thomas Lehnig, Paul Brett, Werner Haas, Patrick Kennedy, Jason Howard, Sriram Vangal, Nitin Borkar, Greg Ruhl, Saurabh Dighe
Issue Date:November 2010
The number of cores integrated onto a single die is expected to climb steadily in the foreseeable future. This move to many-core chips is driven by a need to optimize performance per watt. How best to connect these cores and how to program the resulting ma...
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