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A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm
VLSI Design, International Conference on
By Shailendra Jain, Vasantha Erraguntla, Sriram R. Vangal, Yatin Hoskote, Nitin Borkar, Tulasi Mandepudi, Karthik VP
Issue Date:January 2010
This paper describes energy efficient and reconfigurable fused/continuous Multiply-Accumulator (MAC) architecture for single-precision Floating-point and 16-bit signed integer operands. This eight-stage pipelined and single-cycle throughput MAC design cont...
IA-32 Processor with a Wide-Voltage-Operating Range in 32-nm CMOS
By Gregory Ruhl,Saurabh Dighe,Shailendra Jain,Surhud Khare,Sriram R. Vangal
Issue Date:March 2013
Designing a microprocessor that's efficient across a wide-voltage-operating range requires overcoming a variety of microarchitecture and circuit design challenges. In this article, the authors demonstrate their IA-32 processor, which is built in 32-nm CMOS...
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