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Displaying 1-50 out of 85 total
Secure and Robust Error Correction for Physical Unclonable Functions
Found in: IEEE Design and Test of Computers
By Meng-Day (Mandel) Yu, Srinivas Devadas
Issue Date:January 2010
pp. 48-65
<p>Editor's note:</p><p>Physical unclonable functions (PUFs) offer a promising mechanism that can be used in many security, protection, and digital rights management applications. One key issue is the stability of PUF responses that is of...
 
Controlled Physical Random Functions
Found in: Computer Security Applications Conference, Annual
By Blaise Gassend, Dwaine Clarke, Marten van Dijk, Srinivas Devadas
Issue Date:December 2002
pp. 149
A Physical Random Function (PUF) is a random function that can only be evaluated with the help of a complex physical system. We introduce Controlled Physical Random Functions (CPUFs) which are PUFs that can only be accessed via an algorithm that is physica...
 
Toward a Coherent Multicore Memory Model
Found in: Computer
By Srinivas Devadas
Issue Date:October 2013
pp. 30-31
With exascale multicores, the question of how to efficiently support a shared memory model is of paramount importance. As programmers demand the convenience of coherent shared memory, ever-growing core counts place higher demands on memory subsystems, and ...
 
Optimal and Heuristic Application-Aware Oblivious Routing
Found in: IEEE Transactions on Computers
By Michel A. Kinsy,Myong Hyon Cho,Keun Sup Shim,Mieszko Lis,G. Edward Suh,Srinivas Devadas
Issue Date:January 2013
pp. 59-73
Conventional oblivious routing algorithms do not take into account resource requirements (e.g., bandwidth, latency) of various flows in a given application. As they are not aware of flow demands that are specific to the application, network resources can b...
 
Selecting Spatiotemporal Patterns for Development of Parallel Applications
Found in: IEEE Transactions on Parallel and Distributed Systems
By Henry Hoffmann,Anant Agarwal,Srinivas Devadas
Issue Date:October 2012
pp. 1970-1982
Design patterns for parallel computing attempt to make the field accessible to nonexperts by generalizing the common techniques experts use to develop parallel software. Existing parallel patterns have tremendous descriptive power, but it is often unclear ...
 
Time-Predictable Computer Architecture for Cyber-Physical Systems: Digital Emulation of Power Electronics Systems
Found in: Real-Time Systems Symposium, IEEE International
By Michel Kinsy,Omer Khan,Ivan Celanovic,Dusan Majstorovic,Nikola Celanovic,Srinivas Devadas
Issue Date:December 2011
pp. 305-316
The smart grid concept is a good example of a complex cyber-physical system (CPS) that exhibits intricate interplay between control, sensing, and communication infrastructure on one side, and power processing and actuation on the other side. The more exten...
 
ARCc: A case for an architecturally redundant cache-coherence architecture for large multicores
Found in: Computer Design, International Conference on
By Omer Khan,Henry Hoffmann,Mieszko Lis,Farrukh Hijaz,Anant Agarwal,Srinivas Devadas
Issue Date:October 2011
pp. 411-418
This paper proposes an architecturally redundant cache-coherence architecture (ARCc) that combines the directory and shared-NUCA based coherence protocols to improve performance, energy and dependability. Both coherence mechanisms co-exist in the hardware ...
 
Memory coherence in the age of multicores
Found in: Computer Design, International Conference on
By Mieszko Lis,Keun Sup Shim,Myong Hyon Cho,Srinivas Devadas
Issue Date:October 2011
pp. 1-8
As we enter an era of exascale multicores, the question of efficiently supporting a shared memory model has become of paramount importance. On the one hand, programmers demand the convenience of coherent shared memory; on the other, growing core counts pla...
 
Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System
Found in: International Conference on Field Programmable Logic and Applications
By Michel A. Kinsy,Michael Pellauer,Srinivas Devadas
Issue Date:September 2011
pp. 356-362
Heracles is an open-source complete multicore system written in Verilog. It is fully parameterized and can be reconfigured and synthesized into different topologies and sizes. Each processing node has a fully bypassed, 7-stage pipelined microprocessor runn...
 
Scalable, accurate multicore simulation in the 1000-core era
Found in: Performance Analysis of Systems and Software, IEEE International Symmposium on
By Mieszko Lis, Pengju Ren, Myong Hyon Cho, Keun Sup Shim, Christopher W. Fletcher, Omer Khan, Srinivas Devadas
Issue Date:April 2011
pp. 175-185
We present HORNET, a parallel, highly configurable, cycle-level multicore simulator based on an ingress-queued worm-hole router NoC architecture. The parallel simulation engine offers cycle-accurate as well as periodic synchronization; while preserving fun...
 
Oblivious Routing in On-Chip Bandwidth-Adaptive Networks
Found in: Parallel Architectures and Compilation Techniques, International Conference on
By Myong Hyon Cho, Mieszko Lis, Keun Sup Shim, Michel Kinsy, Tina Wen, Srinivas Devadas
Issue Date:September 2009
pp. 181-190
Oblivious routing can be implemented on simple router hardware, but network performance suffers when routes become congested. Adaptive routing attempts to avoid hot spots by re-routing flows, but requires more complex hardware to determine and configure ne...
 
Static virtual channel allocation in oblivious routing
Found in: Networks-on-Chip, International Symposium on
By Keun Sup Shim, Myong Hyon Cho, Michel Kinsy, Tina Wen, Mieszko Lis, G. Edward Suh, Srinivas Devadas
Issue Date:May 2009
pp. 38-43
Most virtual channel routers have multiple virtual channels to mitigate the effects of head-of-line blocking. When there are more flows than virtual channels at a link, packets or flows must compete for channels, either in a dynamic way at each link or by ...
 
Diastolic arrays: Throughput-driven reconfigurable computing
Found in: Computer-Aided Design, International Conference on
By Myong Hyon Cho, Chih-Chi Cheng, Michel Kinsy, G. Edward Suh, Srinivas Devadas
Issue Date:November 2008
pp. 457-464
Diastolic arrays are arrays of processing elements that communicate exclusively through First-In First-Out (FIFO) queues. FIFO virtualization units enable relaxed timing of data transfers, and include hardware support to guarantee bandwidth and buffer spac...
 
Aegis: A Single-Chip Secure Processor
Found in: IEEE Design and Test of Computers
By G. Edward Suh, Charles W. O'Donnell, Srinivas Devadas
Issue Date:November 2007
pp. 570-580
This article presents the Aegis secure processor architecture, which enables physically secure computing platforms with a main processor as the only trusted component. The Aegis architecture ensures private and authentic program execution even in the face ...
 
Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions
Found in: Computer Architecture, International Symposium on
By G. Edward Suh, Charles W. O'Donnell, Ishan Sachdev, Srinivas Devadas
Issue Date:June 2005
pp. 25-36
Secure processors enable new applications by ensuring private and authentic program execution even in the face of physical attack. In this paper we present the AEGIS secure processor architecture, and evaluate its RTL implementation on FPGAs. By using Phys...
 
Towards Constant Bandwidth Overhead Integrity Checking of Untrusted Data
Found in: Security and Privacy, IEEE Symposium on
By Dwaine Clarke, G. Edward Suh, Blaise Gassend, Ajay Sudan, Marten van Dijk, Srinivas Devadas
Issue Date:May 2005
pp. 139-153
We present an adaptive tree-log scheme to improve the performance of checking the integrity of arbitrarily-large untrusted data, when using only a small fixed-sized trusted state. Currently, hash trees are used to check the data. In many systems that use h...
 
Efficient Memory Integrity Verification and Encryption for Secure Processors
Found in: Microarchitecture, IEEE/ACM International Symposium on
By G. Edward Suh, Dwaine Clarke, Blaise Gassend, Marten van Dijk, Srinivas Devadas
Issue Date:December 2003
pp. 339
Secure processors enable new sets of applications such as commercial grid computing, software copy-protection, and secure mobile agents by providing security from both physical and software attacks. This paper proposes new hardware mechanisms for memory in...
 
Embedded Intelligent SRAM
Found in: Design Automation Conference
By Prabhat Jain, G. Edward Suh, Srinivas Devadas
Issue Date:June 2003
pp. 869
Many embedded systems use a simple pipelined RISC processor for computation and an on-chip SRAM for data storage. We present an enhancement called Intelligent SRAM (ISRAM) that consists of a small computation unit with an accumulator that is placed near th...
 
Caches and Hash Trees for Efficient Memory Integrity Verification
Found in: High-Performance Computer Architecture, International Symposium on
By Blaise Gassend, G.Edward Suh, Dwaine Clarke, Marten van Dijk, Srinivas Devadas
Issue Date:February 2003
pp. 295
<p>We study the hardware cost f implementing hash-tree based verification of untrusted external memory by a high performance processor.This verification could enable applications such as certified program execution.</p> <p>A number of sch...
 
Software-assisted Cache Replacement Mechanisms for Embedded Systems
Found in: Computer-Aided Design, International Conference on
By Prabhat Jain, Srinivas Devadas, Daniel Engels, Larry Rudolph
Issue Date:November 2001
pp. 119
We address the problem of improving cache predictability and performance in embedded systems through the use of software-assisted replacement mechanisms. These mechanisms require additional software controlled state information that affects the cache repla...
 
Observability Analysis of Embedded Software for Coverage-Directed Validation
Found in: Computer-Aided Design, International Conference on
By José C. Costa, Srinivas Devadas, José C. Monteiro
Issue Date:November 2000
pp. 27
The most common approach to checking correctness of a hardware or software design is to verify that a description of the design has the proper behavior as elicited by a series of input stimuli. In the case of software, the program is simply run with the ap...
 
Application-Specific Memory Management for Embedded Systems Using Software-Controlled Caches
Found in: Design Automation Conference
By Larry Rudolph, Prabhat Jain, Srinivas Devadas, Derek Chiou
Issue Date:June 2000
pp. 416-419
We propose a way to improve the performance of embedded processors running data-intensive applications by allowing software to allocate on-chip memory on an application-specific basis. On-chip memory in the form of cache can be made to act like scratch-pad...
 
A Methodology for Accurate Performance Evaluation in Architecture Exploration
Found in: Design Automation Conference
By George Hadjiyiannis, Pietro Russo, Srinivas Devadas
Issue Date:June 1999
pp. 927-932
We present a system that automatically generates a cycle-accurate and bit-true Instruction Level Simulator (ILS) and a hardware implementation model given a description of a target processor. An ILS can be used to obtain a cycle count for a given program r...
 
Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement Coverage
Found in: Design Automation Conference
By Farzan Fallah, Pranav Ashar, Srinivas Devadas
Issue Date:June 1999
pp. 666-671
Validation of RTL circuits remains the primary bottleneck in improving design turnaround time, and simulation remains the primary methodology for validation. Simulation-based validation has suffered from a disconnect between the metrics used to measure the...
 
CAD Techniques for Embedded System Design
Found in: VLSI Design, International Conference on
By Srinivas Devadas, Sharad Malik, Jose Monteiro, Luciano Lavagno
Issue Date:January 1999
pp. 608
No summary available.
   
An Algorithmic Approach To Optimizing Fault Coverage For BIST Logic Synthesis
Found in: Test Conference, International
By Srinivas Devadas, Kurt Keutzer
Issue Date:October 1998
pp. 164
<p>Most approaches to the synthesis of built-in self test (BIST) circuitry use a manual choose-and-evaluate approach, where a particular BISTgenerator is chosenandthen evaluatedby fault-simulating the design with the vectors that the chosen generator...
 
Functional Vector Generation for HDL Models using Linear Programming and 3-Satisfiability
Found in: Design Automation Conference
By Kurt Keutzer, Srinivas Devadas, Farzan Fallah
Issue Date:June 1998
pp. 528-533
Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The HDL model describes interconnections of arithmetic, logic and memory modules. Given a path in the ...
 
OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Verification
Found in: Design Automation Conference
By Kurt Keutzer, Srinivas Devadas, Farzan Fallah
Issue Date:June 1998
pp. 152-157
Functional simulation is still the primary workhorse for verifying the functional correctness of hardware designs. Functional verification is necessarily incomplete because it is not computationally feasible to exhaustively simulate designs. It is importan...
 
Instruction Selection, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator
Found in: Design Automation Conference
By Srinivas Devadas, Silvina Hanono
Issue Date:June 1998
pp. 510-515
The AVIV retargetable code generator produces optimized machine code for target processors with different instruction set architectures AVIV optimizes for minimum code size. Retargetable code generation requires the development of heuristic algorithms for ...
 
Solving Covering Problems Using LPR-Based Lower Bounds
Found in: Design Automation Conference
By Stan Liao, Srinivas Devadas
Issue Date:June 1997
pp. 117
Unate and binate covering problems are a special class of general integer linear programming problems with which several problems in logic synthesis, such as two-level logic minimization and technology mapping, are formulated. Previous branch-and-bound met...
 
ISDL: An Instruction Set Description Language for Retargetability
Found in: Design Automation Conference
By George Hadjiyiannis, Silvina Hanono, Srinivas Devadas
Issue Date:June 1997
pp. 299
We present the Instruction Set Description Language, ISDL, a machine description language used to describe target architectures to a retargetable compiler. The features and flexibility of ISDL enable the description of vastly different architectures, in pa...
 
Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures
Found in: Design Automation Conference
By Ashok Sudarsanam, Stan Liao, Srinivas Devadas
Issue Date:June 1997
pp. 287
Many application-specific architectures provide indirect addressing modes with auto-increment/decrement arithmetic. Since these architectures generally do not feature an indexed addressing mode, stack-allocated variables must be accessed by allocating addr...
 
Scheduling Techniques to Enable Power Management
Found in: Design Automation Conference
By José Monteiro, Srinivas Devadas, Pranav Ashar, Ashutosh Mauskar
Issue Date:June 1996
pp. 349-352
No summary available.
 
Instruction Selection Using Binate Covering for Code Size Optimization
Found in: Computer-Aided Design, International Conference on
By Stan Liao, Srinivas Devadas, Kurt Keutzer, Steve Tjiang
Issue Date:November 1995
pp. 0393
We address the problem of instruction selection in code generation for embedded DSP microprocessors. Such processors have highly irregular data-paths, and conventional code generation methods typically result in inefficient code. Instruction selection can ...
 
Code Optimization Techniques for Embedded DSP Microprocessors
Found in: Design Automation Conference
By Albert Wang, Kurt Keutzer, Srinivas Devadas, Steve Tjiang, Stan Liao
Issue Date:June 1995
pp. 599-604
We address the problem of code optimization for embedded DSP microprocessors. Such processors (e.g., those in the TMS320 series) have highly irregular datapaths, and conventional code generation methods typically result in inefficient code. In this paper w...
 
A Survey of Optimization Techniques Targeting Low Power VLSI Circuits
Found in: Design Automation Conference
By Sharad Malik, Srinivas Devadas
Issue Date:June 1995
pp. 242-247
We survey state-of-the-art optimization methods that target low power dissipation in VLSI circuits. Optimizations at the circuit, logic, architectural and system levels are considered.
 
Power modeling and other new features in the Graphite simulator
Found in: 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)
By George Kurian,Sabrina M. Neuman,George Bezerra,Anthony Giovinazzo,Srinivas Devadas,Jason E. Miller
Issue Date:March 2014
pp. 132-134
This paper described recent improvements to the Graphite simulator designed to help explore current and emerging research topics. With these improvements, Graphite is ideally suited to explore both power and performance in future multicore and manycore pro...
   
Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs
Found in: 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)
By Christopher W. Fletchery,Ling Ren,Xiangyao Yu,Marten Van Dijk,Omer Khan,Srinivas Devadas
Issue Date:February 2014
pp. 213-224
Oblivious RAM (ORAM) is an established cryptographic technique to hide a program's address pattern to an untrusted storage system. More recently, ORAM schemes have been proposed to replace conventional memory controllers in secure processor settings to pro...
   
Locality-aware data replication in the Last-Level Cache
Found in: 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)
By George Kurian,Srinivas Devadas,Omer Khan
Issue Date:February 2014
pp. 1-12
Next generation multicores will process massive data with varying degree of locality. Harnessing on-chip data locality to optimize the utilization of cache and network resources is of fundamental importance. We propose a locality-aware selective data repli...
   
Thread Migration Prediction for Distributed Shared Caches
Found in: IEEE Computer Architecture Letters
By Keun Sup Shim,Mieszko Lis,Omer Khan,Srinivas Devadas
Issue Date:January 2014
pp. 1-1
Chip-multiprocessors (CMPs) have become the mainstream parallel architecture in recent years; for scalability reasons, designs with high core counts tend towards tiled CMPs with physically distributed shared caches. This naturally leads to a Non-Uniform Ca...
 
An Observability-Based Code Coverage Metric for Functional Simulation
Found in: Computer-Aided Design, International Conference on
By Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer
Issue Date:November 1996
pp. 418
Functional simulation is the most widely used method for design verification. At various levels of abstraction, e.g., behavioral, register-transfer level and gate level, the designer simulates the design using a large number of vectors attempting to debug ...
 
Generalized external interaction with tamper-resistant hardware with bounded information leakage
Found in: Proceedings of the 2013 ACM workshop on Cloud computing security workshop (CCSW '13)
By Srinivas Devadas, Xiangyao Yu, Christopher W. Fletcher, Ling Ren, Marten van Dijk
Issue Date:November 2013
pp. 23-34
This paper investigates secure ways to interact with tamper-resistant hardware leaking a strictly bounded amount of information. Architectural support for the interaction mechanisms is studied and performance implications are evaluated. The interaction mec...
     
Authenticated storage using small trusted hardware
Found in: Proceedings of the 2013 ACM workshop on Cloud computing security workshop (CCSW '13)
By Hsin-Jung Yang, Srinivas Devadas, Nickolai Zeldovich, Victor Costan
Issue Date:November 2013
pp. 35-46
A major security concern with outsourcing data storage to third-party providers is authenticating the integrity and freshness of data. State-of-the-art software-based approaches require clients to maintain state and cannot immediately detect forking attack...
     
Path ORAM: an extremely simple oblivious RAM protocol
Found in: Proceedings of the 2013 ACM SIGSAC conference on Computer & communications security (CCS '13)
By Elaine Shi, Srinivas Devadas, Christopher Fletcher, Emil Stefanov, Ling Ren, Marten van Dijk, Xiangyao Yu
Issue Date:November 2013
pp. 299-310
We present Path ORAM, an extremely simple Oblivious RAM protocol with a small amount of client storage. Partly due to its simplicity, Path ORAM is the most practical ORAM scheme for small client storage known to date. We formally prove that Path ORAM requi...
     
Design space exploration and optimization of path oblivious RAM in secure processors
Found in: Proceedings of the 40th Annual International Symposium on Computer Architecture (ISCA '13)
By Christopher W. Fletcher, Ling Ren, Marten van Dijk, Srinivas Devadas, Xiangyao Yu
Issue Date:June 2013
pp. 571-582
Keeping user data private is a huge problem both in cloud computing and computation outsourcing. One paradigm to achieve data privacy is to use tamper-resistant processors, inside which users' private data is decrypted and computed upon. These processors n...
     
The locality-aware adaptive cache coherence protocol
Found in: Proceedings of the 40th Annual International Symposium on Computer Architecture (ISCA '13)
By George Kurian, Omer Khan, Srinivas Devadas
Issue Date:June 2013
pp. 523-534
Next generation multicore applications will process massive amounts of data with significant sharing. Data movement and management impacts memory access latency and consumes power. Therefore, harnessing data locality is of fundamental importance in future ...
     
A secure processor architecture for encrypted computation on untrusted programs
Found in: Proceedings of the seventh ACM workshop on Scalable trusted computing (STC '12)
By Christopher W. Fletcher, Marten van Dijk, Srinivas Devadas
Issue Date:October 2012
pp. 3-8
This paper considers encrypted computation where the user specifies encrypted inputs to an untrusted program, and the server computes on those encrypted inputs. To this end we propose a secure processor architecture, called Ascend, that guarantees privacy ...
     
Towards an interpreter for efficient encrypted computation
Found in: Proceedings of the 2012 ACM Workshop on Cloud computing security workshop (CCSW '12)
By Christopher W. Fletcher, Marten van Dijk, Srinivas Devadas
Issue Date:October 2012
pp. 83-94
Fully homomorphic encryption (FHE) techniques are capable of performing encrypted computation on Boolean circuits, i.e., the user specifies encrypted inputs to the program, and the server computes on the encrypted inputs. Applying these techniques to gener...
     
A low-overhead dynamic optimization framework for multicores
Found in: Proceedings of the 21st international conference on Parallel architectures and compilation techniques (PACT '12)
By Christopher W. Fletcher, Omer Khan, Rachael Harding, Srinivas Devadas
Issue Date:September 2012
pp. 467-468
This paper argues for a "less is more" design philosophy when integrating dynamic optimization into a multicore system. The primary insight is that dynamic optimization is inherently loosely-coupled and can therefore be supported on multicores with very lo...
     
Brief announcement: distributed shared memory based on computation migration
Found in: Proceedings of the 23rd ACM symposium on Parallelism in algorithms and architectures (SPAA '11)
By Christopher W. Fletcher, Ilia Lebedev, Keun Sup Shim, Michel Kinsy, Mieszko Lis, Myong Hyon Cho, Omer Khan, Srinivas Devadas
Issue Date:June 2011
pp. 253-256
We consider the interactive model of recommender systems, in which users are asked about just a few of their preferences, and in return the system outputs an approximation of all their preferences. The measure of performance is the probe complexity of the ...
     
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