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Displaying 1-16 out of 16 total
Regional Consistency: Programmability and Performance for Non-cache-coherent Systems
Found in: 2013 12th IEEE International Conference on Trust, Security and Privacy in Computing and Communications (TrustCom)
By Bharath Ramesh,Calvin J. Ribbens,Srinidhi Varadarajan
Issue Date:July 2013
pp. 941-948
Parallel programmers face the often irreconcilable goals of programmability and performance. HPC systems use distributed memory for scalability, thereby sacrificing the programmability advantages of shared memory programming models. Furthermore, the rapid ...
 
Towards Virtual Shared Memory for Non-cache-coherent Multicore Systems
Found in: 2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW)
By Bharath Ramesh,Calvin J. Ribbens,Srinidhi Varadarajan
Issue Date:May 2013
pp. 1186-1193
Emerging heterogeneous architectures do not necessarily provide cache-coherent shared memory across all components of the system. Although there are good reasons for this architectural decision, it does provide programmers with a challenge. Several program...
 
Open Network Emulator: A Parallel Direct Code Execution Network Simulator
Found in: 2012 ACM/IEEE/SCS 26th Workshop on Principles of Advanced and Distributed Simulation (PADS)
By Vedavyas Duggirala,Srinidhi Varadarajan
Issue Date:July 2012
pp. 101-110
In this paper, we present the Open Network Emulator (ONE) a network simulator that combines the controllability and scalability of simulation with the direct code execution properties of emulation and experimental test beds. ONE has two novel features. Fir...
 
Is It Time to Rethink Distributed Shared Memory Systems?
Found in: Parallel and Distributed Systems, International Conference on
By Bharath Ramesh,Calvin J. Ribbens,Srinidhi Varadarajan
Issue Date:December 2011
pp. 212-219
We present core elements of Samhita, a new user level software distributed shared memory (DSM) system. Our work is motivated by two observations. First, the rise of many-core architectures is producing a growing emphasis on threaded codes to achieve perfor...
 
Tempest: A portable tool to identify hot spots in parallel code
Found in: Parallel Processing, International Conference on
By Kirk W. Cameron, Hari K. Pyla, Srinidhi Varadarajan
Issue Date:September 2007
pp. 37
Compute clusters are consuming more power at higher densities than ever before. This results in increased thermal dissipation, the need for powerful cooling systems, and ultimately a reduction in system reliability as temperatures increase. Over the past s...
 
DejaVu: Transparent User-Level Checkpointing, Migration, and Recovery for Distributed Systems
Found in: Parallel and Distributed Processing Symposium, International
By Joseph F. Ruscio, Michael A. Heffner, Srinidhi Varadarajan
Issue Date:March 2007
pp. 119
In this paper, we present a new fault tolerance system called DejaVu for transparent and automatic checkpointing, migration, and recovery of parallel and distributed applications. DejaVu provides a transparent parallel checkpointing and recovery mechanism ...
 
The Weaves Runtime Framework
Found in: Parallel and Distributed Processing Symposium, International
By Srinidhi Varadarajan
Issue Date:April 2004
pp. 197b
<p>This paper presents a language independent runtime framework - called Weaves - for object based composition of unmodified code modules that enables . arbitrary (selective) sharing of state between multiple control flows through a process. Furtherm...
   
Adaptive Code Collage: A Framework to Transparently Modify Scientific Codes
Found in: Computing in Science and Engineering
By Pilsung Kang,Naren Ramakrishnan,Calvin J. Ribbens,Srinidhi Varadarajan,Michael Heffner
Issue Date:January 2012
pp. 52-63
Legacy scientific codes are often repurposed to fit adaptive needs, but making such code adaptive without changing the original source programs can be challenging. Adaptive Code Collage (ACC) meets this challenge using function-call interception in a langu...
 
The Adaptive Code Kitchen: Flexible Tools for Dynamic Application Composition
Found in: Parallel and Distributed Processing Symposium, International
By Pilsung Kang, Mike Heffner, Joy Mukherjee, Naren Ramakrishnan, Srinidhi Varadarajan, Cal Ribbens, Danesh K. Tafti
Issue Date:March 2007
pp. 303
Driven by the increasing componentization of scientific codes, the deployment of high-end system infrastructures such as the Grid, and the desire to support high level problem solving primitives, application composition systems have become prevalent in com...
 
The Distributed Open Network Emulator: Using Relativistic Time for Distributed Scalable Simulation
Found in: Parallel and Distributed Simulation, Workshop on
By Craig Bergstrom, Srinidhi Varadarajan, Godmar Back
Issue Date:May 2006
pp. 19-28
In this paper, we present the design and implementation of The Distributed Open Network Emulator (dONE), a scalable hybrid network emulation/simulation environment. It has several novel contributions. First, a new model of time called relativistic time tha...
   
Transparent runtime deadlock elimination
Found in: Proceedings of the 21st international conference on Parallel architectures and compilation techniques (PACT '12)
By Hari K. Pyla, Srinidhi Varadarajan
Issue Date:September 2012
pp. 477-478
Thread based concurrent programming is hard due to the potential of concurrency bugs (e.g., data races, atomicity violations, deadlocks, and order violations). While data races and atomicity violations can be ameliorated with appropriate synchronization (a...
     
Maintainable and reusable scientific software adaptation: democratizing scientific software adaptation
Found in: Proceedings of the tenth international conference on Aspect-oriented software development (AOSD '11)
By Eli Tilevich, Naren Ramakrishnan, Pilsung Kang, Srinidhi Varadarajan
Issue Date:March 2011
pp. 165-176
Scientific software must be adapted for different execution environments, problem sets, and available resources to ensure its efficiency and reliability. Although adaptation patterns can be found in a sizable percentage of recent scientific applications, t...
     
Avoiding deadlock avoidance
Found in: Proceedings of the 19th international conference on Parallel architectures and compilation techniques (PACT '10)
By Hari K. Pyla, Srinidhi Varadarajan
Issue Date:September 2010
pp. 75-86
The evolution of processor architectures from single core designs with increasing clock frequencies to multi-core designs with relatively stable clock frequencies has fundamentally altered application design. Since application programmers can no longer rel...
     
Modular implementation of adaptive decisions in stochastic simulations
Found in: Proceedings of the 2009 ACM symposium on Applied Computing (SAC '09)
By Calvin J. Ribbens, Naren Ramakrishnan, Pilsung Kang, Srinidhi Varadarajan, Yang Cao
Issue Date:March 2009
pp. 1-5
We present a modular approach to implement adaptive decisions with existing scientific codes. Using a sophisticated system software tool based on the function call interception technique, an external code module is transparently combined with the given pro...
     
Develop once deploy anywhere achieving adaptivity with a runtime linker/loader framework
Found in: Proceedings of the 4th workshop on Reflective and adaptive middleware systems (ARM '05)
By Joy Mukherjee, Srinidhi Varadarajan
Issue Date:November 2005
pp. 1-6
This paper presents Load and Let Link -- a framework for flexible runtime loading and linking of procedural native code components. LLL has several novel aspects. First, it provides componentization without requiring an object-oriented language. Second, LL...
     
Design and evaluation of a DRAM-based shared memory ATM switch
Found in: Proceedings of the 1997 ACM SIGMETRICS international conference on Measurement and modeling of computer systems (SIGMETRICS '97)
By Srinidhi Varadarajan, Tzi-cker Chiueh
Issue Date:June 1997
pp. 261-269
Beluga is a single-chip switch architecture specifically targeted at local area ATM networks, and it features three architectural innovations. First, an interconnection hierarchy composed of multiple switching fabrics is built into the chip to provide both...
     
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