Search For:

Displaying 1-2 out of 2 total
Phase-Guided Scheduling on Single-ISA Heterogeneous Multicore Processors
Found in: Digital Systems Design, Euromicro Symposium on
By Lina Sawalha,Sonya Wolff,Monte P. Tull,Ronald D. Barnes
Issue Date:September 2011
pp. 736-745
Single-ISA heterogeneous (also known as asymmetric) multicore processors offer significant advantages over homogenous multicores in terms of both power and performance. Power-efficient cores can be paired with higher-performance cores to achieve advantageo...
Revisiting Using the Results of Pre-Executed Instructions in Runahead Processors
Found in: IEEE Computer Architecture Letters
By Sonya Wolff,Ronald Barnes
Issue Date:September 2013
pp. 1
Long-latency cache accesses cause significant performance-impacting delays for both in-order and out-of-order processor systems. To address these delays, runahead pre-execution has been shown to produce speedups by warming-up cache structures during stalls...