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Displaying 1-3 out of 3 total
EVAL: Utilizing processors with variation-induced timing errors
Microarchitecture, IEEE/ACM International Symposium on
By Smruti Sarangi, Brian Greskamp, Abhishek Tiwari, Josep Torrellas
Issue Date:November 2008
Parameter variation in integrated circuits causes sections of a chip to be slower than others. If, to prevent any resulting timing errors, we design processors for worst-case parameter values, we may lose substantial performance. An alternate approach expl...
Patching Processor Design Errors with Programmable Hardware
By Smruti Sarangi, Satish Narayanasamy, Bruce Carneal, Abhishek Tiwari, Brad Calder, Josep Torrellas
Issue Date:January 2007
Equipping processors with programmable hardware to patch design errors lets manufacturers release regular hardware patches, avoiding costly chip recalls and potentially speeding time to market. For each error detected, the manufacturer creates a fingerprin...
FP-NUCA: A Fast NOC Layer for Implementing Large NUCA Caches
IEEE Transactions on Parallel and Distributed Systems
By Anuj Arora,Mayur Harne,Hameedah Sultan,Akriti Bagaria,Smruti Sarangi
Issue Date:February 2015
NUCA caches have traditionally been proposed as a solution for mitigating wire delays, and delays introduced due to complex networks on chip. Traditional approaches have reported significant performance gains with intelligent block placement, location, rep...
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