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Displaying 1-13 out of 13 total
Exploring hardware support for scaling irregular applications on multi-node multi-core architectures
Found in: 2013 IEEE 24th International Conference on Application-specific Systems, Architectures and Processors (ASAP)
By Simone Secchi,Marco Ceriani,Antonino Tumeo,Oreste Villa,Gianluca Palermo,Luigi Raffo
Issue Date:June 2013
pp. 309-313
The recent emergence of large-scale knowledge discovery, data mining and social network analysis, irregular applications have gained renewed interest. Cache-based architectures do not provide optimal performances with such workloads, mainly due to the low ...
 
Exploring Manycore Multinode Systems for Irregular Applications with FPGA Prototyping
Found in: 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
By Marco Ceriani,Gianluca Palermo,Simone Secchi,Antonino Tumeo,Oreste Villa
Issue Date:April 2013
pp. 238
Knowledge discovery applications are an emerging class of irregular applications that exploit graph-based data structures, present poor locality and analyze very big data sets that require multi-node systems for processing. Current clusters, which exploit ...
 
Fast and Accurate Simulation of the Cray XMT Multithreaded Supercomputer
Found in: IEEE Transactions on Parallel and Distributed Systems
By Oreste Villa,Antonino Tumeo,Simone Secchi,Joseph B. Manzano
Issue Date:December 2012
pp. 2266-2279
Irregular applications, such as data mining or graph-based computations, show unpredictable memory/network access patterns and control structures. Massively multithreaded architectures with large processor counts, like the Cray MTA-1, MTA-2, and XMT, appea...
 
Efficient Sorting on the Tilera Manycore Architecture
Found in: 2012 24th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)
By Alessandro Morari,Antonino Tumeo,Oreste Villa,Simone Secchi,Mateo Valero
Issue Date:October 2012
pp. 171-178
We present an efficient implementation of the radix sort algorithm for the Tilera TILEPro64 processor. The TILEPro64 is one of the first successful commercial manycore processors. It is composed of 64 tiles interconnected through multiple fast Networks-on-...
 
Designing Next-Generation Massively Multithreaded Architectures for Irregular Applications
Found in: Computer
By Antonino Tumeo,Simone Secchi,Oreste Villa
Issue Date:August 2012
pp. 53-61
Massively multithreaded architectures like the Cray XMT address the needs of irregular data-intensive applications better than commodity clusters. A proposed evolution of the XMT integrates multicore processors and next-generation interconnects, along with...
 
A Bandwidth-Optimized Multi-core Architecture for Irregular Applications
Found in: Cluster Computing and the Grid, IEEE International Symposium on
By Simone Secchi,Antonino Tumeo,Oreste Villa
Issue Date:May 2012
pp. 580-587
This paper presents an architecture for high performance computing systems specifically targeted to irregular applications. We show how a multi-core paradigm can benefit from next-generation memories and networks, while still resorting to fine-grained mult...
 
Contention Modeling for Multithreaded Distributed Shared Memory Machines: The Cray XMT
Found in: Cluster Computing and the Grid, IEEE International Symposium on
By Simone Secchi, Antonino Tumeo, Oreste Villa
Issue Date:May 2011
pp. 275-284
Distributed Shared Memory (DSM) machines are a wide class of multi-processor computing systems where a large virtually-shared address space is mapped on a network of physically distributed memories. High memory latency and network contention are two of the...
 
A Network on Chip Architecture for Heterogeneous Traffic Support with Non-Exclusive Dual-Mode Switching
Found in: Digital Systems Design, Euromicro Symposium on
By Simone Secchi, Francesca Palumbo, Danilo Pani, Luigi Raffo
Issue Date:September 2008
pp. 141-148
As the multi-core processors era took place, several design concerns have risen. Interconnection layer efficiency has gained particular relevance as a crucial issue to be addressed in order to leverage the large amount of on-chip resources that today's VLS...
 
Exploring Efficient Hardware Support for Applications with Irregular Memory Patterns on Multinode Manycore Architectures
Found in: IEEE Transactions on Parallel and Distributed Systems
By Marco Ceriani,Simone Secchi,Oreste Villa,Antonino Tumeo,Gianluca Palermo
Issue Date:August 2014
pp. 1
With computing systems becoming ubiquitous, numerous data sets of extremely large size are becoming available for analysis. Often the data collected have complex, graph based structures, which makes them difficult to process with traditional tools. Moreove...
 
Second Workshop on Irregular Applications: Architectures & Algorithms - IA 3 2012
Found in: 2012 SC Companion: High-Performance Computing, Networking, Storage and Analysis (SCC)
By John Feo,Antonino Tumeo,Oreste Villa,Simone Secchi,Mahantesh Halappanavar
Issue Date:November 2012
pp. lxiv-lxv
This workshop, this year in its second edition, aims at bringing together scientists with all these different backgrounds to discuss, define and design methods and technologies for efficiently supporting irregular applications on current and future machine...
   
Prototyping hardware support for irregular applications
Found in: Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO '13)
By Antonino Tumeo, Marco Ceriani, Oreste Villa, Simone Secchi
Issue Date:January 2013
pp. 1-8
The use of FPGA platforms developed with off-the-shelf soft cores has recently emerged as one of the most promising fast prototyping approaches to design, evaluate and validate new architectural components for multi- and many-core processors. The approach ...
     
Towards efficient execution of irregular applications: panel outline
Found in: Proceedings of the first workshop on Irregular applications: architectures and algorithm (IAAA '11)
By Antonino Tumeo, John Feo, Oreste Villa, Simone Secchi
Issue Date:November 2011
pp. 43-44
This panel seeks to discuss the current challenges for the efficient execution of irregular applications and to propose directions for the development of next generation systems.
     
Irregular applications: architectures & algorithms
Found in: Proceedings of the first workshop on Irregular applications: architectures and algorithm (IAAA '11)
By Antonino Tumeo, John Feo, Oreste Villa, Simone Secchi
Issue Date:November 2011
pp. 1-2
Irregular applications are characterized by irregular data structures, control and communication patterns. Novel irregular high performance applications which deal with large data sets and require have recently appeared. Unfortunately, current high perform...
     
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