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Displaying 1-9 out of 9 total
Eliminating voltage emergencies via software-guided code transformations
Found in: ACM Transactions on Architecture and Code Optimization (TACO)
By David Brooks, Gu-Yeon Wei, Gu-Yeon Wei, Kim Hazelwood, Kim Hazelwood, Meeta S. Gupta, Meeta S. Gupta, Michael D. Smith, Michael D. Smith, Simone Campanoni, Simone Campanoni, Vijay Janapa Reddi, Vijay Janapa Reddi
Issue Date:September 2010
pp. 1-28
In recent years, circuit reliability in modern high-performance processors has become increasingly important. Shrinking feature sizes and diminishing supply voltages have made circuits more sensitive to microprocessor supply voltage fluctuations. These flu...
Helix: Making the Extraction of Thread-Level Parallelism Mainstream
Found in: IEEE Micro
By Simone Campanoni,Timothy M. Jones,Glenn Holloway,Gu-Yeon Wei,David Brooks
Issue Date:July 2012
pp. 8-18
Improving system performance increasingly depends on exploiting microprocessor parallelism, yet mainstream compilers still don't parallelize code automatically. Helix automatically parallelizes general-purpose programs without requiring any ...
Static memory management within bytecode languages on multicore systems
Found in: Computing in Heterogeneous, Autonomous 'N' Goal-Oriented Environments, International Workshop on
By Simone Campanoni,Luca Rocchini
Issue Date:March 2011
pp. 1-8
Object-code virtualization, commonly used to achieve software portability, relies on a virtual execution environment, typically comprising an interpreter used for initial execution of methods, and a JIT for native code generation. The availability of multi...
Voltage Noise in Production Processors
Found in: IEEE Micro
By Vijay Janapa Reddi, Svilen Kanev, Wonyoung Kim, Simone Campanoni, Michael D. Smith, Gu-Yeon Wei, David Brooks
Issue Date:January 2011
pp. 20-28
<p>Voltage variations are a major challenge in processor design. Here, researchers characterize the voltage noise characteristics of programs as they run to completion on a production Core 2 Duo processor. Furthermore, they characterize the implicati...
Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Vijay Janapa Reddi, Svilen Kanev, Wonyoung Kim, Simone Campanoni, Michael D. Smith, Gu-Yeon Wei, David Brooks
Issue Date:December 2010
pp. 77-88
Parameter variations have become a dominant challenge in microprocessor design. Voltage variation is especially daunting because it happens so rapidly. We measure and characterize voltage variation in a running Intel Core2 Duo processor. By sensing on-die ...
Models and Tradeoffs in WSN System-Level Design
Found in: Digital Systems Design, Euromicro Symposium on
By Simone Campanoni, William Fornaciari
Issue Date:September 2008
pp. 676-684
System-level design of WSNs includes the selection of the sensing nodes and their dissemination in the environment to be monitored. Many design choices have to be taken during this stage of the development of the application. The goal of this paper is to p...
HELIX-RC: An architecture-compiler co-design for automatic parallelization of irregular programs
Found in: 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)
By Simone Campanoni,Kevin Brownell,Svilen Kanev,Timothy M. Jones,Gu-Yeon Wei,David Brooks
Issue Date:June 2014
pp. 217-228
Data dependences in sequential programs limit parallelization because extracted threads cannot run independently. Although thread-level speculation can avoid the need for precise dependence analysis, communication overheads required to synchronize actual d...
Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack
Found in: Proceedings of the 46th Annual Design Automation Conference (DAC '09)
By David Brooks, Gu-yeon Wei, Meeta S. Gupta, Michael D. Smith, Simone Campanoni, Vijay Janapa Reddi
Issue Date:July 2009
pp. 788-793
Power constrained designs are becoming increasingly sensitive to supply voltage noise. We propose a hardware-software collaborative approach to enable aggressive operating margins: a checkpoint-recovery mechanism corrects margin violations, while a run-tim...
Just-In-Time compilation on ARM processors
Found in: Proceedings of the 4th workshop on the Implementation, Compilation, Optimization of Object-Oriented Languages and Programming Systems (ICOOOLPS '09)
By Giovanni Agosta, Michele Tartara, Simone Campanoni, Stefano Crespi Reghizzi
Issue Date:July 2009
pp. 70-73
This paper presents a Just-In-Time compilation system for ARM processors. The complete architecture is described, starting from static compilation of the sources into CIL (Common Intermediate Language) bytecode. The intermediate languages that are used are...