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Displaying 1-22 out of 22 total
A Quantitative, Experimental Approach to Measuring Processor Side-Channel Security
Found in: IEEE Micro
By John Demme,Robert Martin,Adam Waksman,Simha Sethumadhavan
Issue Date:May 2013
pp. 68-77
User inputs tend to change the execution characteristics of applications including their interactions with cache, network, storage, and other systems. Many attacks have exploited the observable side effects of these execution characteristics to expose sens...
 
The MEERKATS Cloud Security Architecture
Found in: 2012 32nd International Conference on Distributed Computing Systems Workshops (ICDCS Workshops)
By Angelos D. Keromytis,Roxana Geambasu,Simha Sethumadhavan,Salvatore J. Stolfo,Junfeng Yang,Azzedine Benameur,Marc Dacier,Matthew Elder,Darrell Kienzle,Angelos Stavrou
Issue Date:June 2012
pp. 446-450
MEERKATS is a novel architecture for cloud environments that elevates continuous system evolution and change as first-rate design principles. Our goal is to enable an environment for cloud services that constantly changes along several dimensions, toward c...
 
A Case for Hybrid Discrete-Continuous Architectures
Found in: IEEE Computer Architecture Letters
By Simha Sethumadhavan,Ryan Roberts,Yannis Tsividis
Issue Date:January 2012
pp. 1-4
Current technology trends indicate that power- and energyefficiency will limit chip throughput in the future. Current solutions to these problems, either in the way of programmable or fixed-function digital accelerators will soon reach their limits as micr...
 
The SPARCHS Project: Hardware Support for Software Security
Found in: SysSec Workshop
By Simha Sethumadhavan,Salvatore J. Stolfo,Angelos Keromytis,Junfeng Yang,David August
Issue Date:July 2011
pp. 119-122
This paper describes the SPARCHS project at Columbia and Princeton Universities. Drawing inspiration from biological defenses, this project aims to enhance security with clean-slate design of hardware. The ideas to be explored in the project and current st...
 
Silencing Hardware Backdoors
Found in: Security and Privacy, IEEE Symposium on
By Adam Waksman, Simha Sethumadhavan
Issue Date:May 2011
pp. 49-63
Hardware components can contain hidden backdoors, which can be enabled with catastrophic effects or for ill-gotten profit. These backdoors can be inserted by a malicious insider on the design team or a third-party IP provider. In this paper, we propose tec...
 
Tamper Evident Microprocessors
Found in: Security and Privacy, IEEE Symposium on
By Adam Waksman, Simha Sethumadhavan
Issue Date:May 2010
pp. 173-188
Most security mechanisms proposed to date unquestioningly place trust in microprocessor hardware. This trust, however, is misplaced and dangerous because microprocessors are vulnerable to insider attacks that can catastrophically compromise security, integ...
 
COMPASS: A Community-driven Parallelization Advisor for Sequential Software
Found in: Multicore Software Engineering, ICSE Workshop on
By Simha Sethumadhavan, Nipun Arora, Ravindra Babu Ganapathi, John Demme, Gail E. Kaiser
Issue Date:May 2009
pp. 41-48
The widespread adoption of multicores has renewed the emphasis on the use of parallelism to improve performance. The present and growing diversity in hardware architectures and software environments, however, continues to pose difficulties in the effective...
 
Distributed Pagerank for P2P Systems
Found in: High-Performance Distributed Computing, International Symposium on
By Karthikeyan Sankaralingam, Simha Sethumadhavan, James C. Browne
Issue Date:June 2003
pp. 58
<p>This paper de.nes and describes a fully distributed implementation of Google?s highly effective Pagerank algorithm, for
 
Composable Lightweight Processors
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Changkyu Kim, Simha Sethumadhavan, M.S. Govindan, Nitya Ranganathan, Divya Gulati, Doug Burger, Stephen W. Keckler
Issue Date:December 2007
pp. 381-394
Modern chip multiprocessors (CMPs) are designed to exploit both instruction-level parallelism (ILP) within pro- cessors and thread-level parallelism (TLP) within and across processors. However, the number of processors and the granularity of each processor...
 
Distributed Microarchitectural Protocols in the TRIPS Prototype Processor
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Karthikeyan Sankaralingam, Ramadass Nagarajan, Robert McDonald, Rajagopalan Desikan, Saurabh Drolia, M.S. Govindan, Paul Gratz, Divya Gulati, Heather Hanson, Changkyu Kim, Haiming Liu, Nitya Ranganathan, Simha Sethumadhavan, Sadia Sharif, Premkishore Shiva
Issue Date:December 2006
pp. 480-491
Growing on-chip wire delays will cause many future microarchitectures to be distributed, in which hardware resources within a single processor become nodes on one or more switched micronetworks. Since large processor cores will require multiple clock cycle...
 
Scalable Hardware Memory Disambiguation for High-ILP Processors
Found in: IEEE Micro
By Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler
Issue Date:November 2004
pp. 118-127
Power is a major problem for scaling the hardware needed to support memory disambiguation in future out-of-order architectures. In current machines, the traditional detection of memory ordering violations requires frequent associative searches of state pro...
 
Scalable Hardware Memory Disambiguation for High ILP Processors
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler
Issue Date:December 2003
pp. 399
This paper describes several methods for improving the scalability of memory disambiguation hardware for future high ILP processors. As the number of in-flight instructions grows with issue width and pipeline depth, the load/store queues (LSQ) threaten to ...
 
FANCI: identification of stealthy malicious logic using boolean functional analysis
Found in: Proceedings of the 2013 ACM SIGSAC conference on Computer & communications security (CCS '13)
By Simha Sethumadhavan, Adam Waksman, Matthew Suozzo
Issue Date:November 2013
pp. 697-708
Hardware design today bears similarities to software design. Often vendors buy and integrate code acquired from third-party organizations into their designs, especially in embedded/system-on-chip designs. Currently, there is no way to determine if third-pa...
     
On the feasibility of online malware detection with performance counters
Found in: Proceedings of the 40th Annual International Symposium on Computer Architecture (ISCA '13)
By Adam Waksman, Adrian Tang, Jared Schmitz, John Demme, Matthew Maycock, Salvatore Stolfo, Simha Sethumadhavan
Issue Date:June 2013
pp. 559-570
The proliferation of computers in any domain is followed by the proliferation of malware in that domain. Systems, including the latest mobile platforms, are laden with viruses, rootkits, spyware, adware and other classes of malware. Despite the existence o...
     
Hardware enhanced security
Found in: Proceedings of the 2012 ACM conference on Computer and communications security (CCS '12)
By G. Edward Suh, Ruby Lee, Simha Sethumadhavan
Issue Date:October 2012
pp. 1052-1052
Building a secure computing system requires careful coordination among all layers in the system from hardware to software. Even if secure by itself, a higher layer protection mechanism may be bypassed if lower layer software or hardware is vulnerable. Addi...
     
TimeWarp: rethinking timekeeping and performance monitoring mechanisms to mitigate side-channel attacks
Found in: Proceedings of the 39th Annual International Symposium on Computer Architecture (ISCA '12)
By John Demme, Robert Martin, Simha Sethumadhavan
Issue Date:June 2012
pp. 118-129
Over the past two decades, several microarchitectural side channels have been exploited to create sophisticated security attacks. Solutions to this problem have mainly focused on fixing the source of leaks either by limiting the flow of information through...
     
Side-channel vulnerability factor: a metric for measuring information leakage
Found in: Proceedings of the 39th Annual International Symposium on Computer Architecture (ISCA '12)
By Adam Waksman, John Demme, Robert Martin, Simha Sethumadhavan
Issue Date:June 2012
pp. 106-117
There have been many attacks that exploit side-effects of program execution to expose secret information and many proposed countermeasures to protect against these attacks. However there is currently no systematic, holistic methodology for understanding in...
     
Approximate graph clustering for program characterization
Found in: ACM Transactions on Architecture and Code Optimization (TACO)
By Simha Sethumadhavan, John Demme
Issue Date:January 2012
pp. 1-21
An important aspect of system optimization research is the discovery of program traits or behaviors. In this paper, we present an automated method of program characterization which is able to examine and cluster program graphs, i.e., dynamic data graphs or...
     
Rapid identification of architectural bottlenecks via precise event counting
Found in: Proceeding of the 38th annual international symposium on Computer architecture (ISCA '11)
By John Demme, Simha Sethumadhavan
Issue Date:June 2011
pp. 353-364
On-chip performance counters play a vital role in computer architecture research due to their ability to quickly provide insights into application behaviors that are time consuming to characterize with traditional methods. The usefulness of modern performa...
     
Multitasking workload scheduling on flexible-core chip multiprocessors
Found in: Proceedings of the 17th international conference on Parallel architectures and compilation techniques (PACT '08)
By Changkyu Kim, Divya P. Gulati, Doug Burger, Simha Sethumadhavan, Stephen W. Keckler
Issue Date:October 2008
pp. 133-133
While technology trends have ushered in the age of chip multiprocessors (CMP), a fundamental question is what size to make each core. Most current commercial designs are symmetric CMPs (SCMP) in which each core is identical and range from a simple RISC pro...
     
Late-binding: enabling unordered load-store queues
Found in: Proceedings of the 34th annual international symposium on Computer architecture (ISCA '07)
By Doug Burger, Franziska Roesner, Joel S. Emer, Simha Sethumadhavan, Stephen W. Keckler
Issue Date:June 2007
pp. 347-357
Conventional load/store queues (LSQs) are an impediment to both power-efficient execution in superscalar processors and scaling tolarge-window designs. In this paper, we propose techniques to improve the area and power efficiency of LSQs by allocating entr...
     
Scalable selective re-execution for EDGE architectures
Found in: Proceedings of the 11th international conference on Architectural support for programming languages and operating systems (ASPLOS-XI)
By Doug Burger, Rajagopalan Desikan, Simha Sethumadhavan, Stephen W. Keckler
Issue Date:October 2004
pp. 97-105
Pipeline flushes are becoming increasingly expensive in modern microprocessors with large instruction windows and deep pipelines. Selective re-execution is a technique that can reduce the penalty of mis-speculations by re-executing only instructions affect...
     
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