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Displaying 1-13 out of 13 total
Static Transition Probability Analysis Under Uncertainty
Found in: Computer Design, International Conference on
By Siddharth Garg, Siddharth Tata, Ravishankar Arunachalam
Issue Date:October 2004
pp. 380-386
Deterministic gate delay models have been widely used to find the transition probabilities at the nodes of a circuit for calculating the power dissipation. However, with progressive scaling down of feature sizes, the variations in process parameters increa...
 
3D-GCP: An analytical model for the impact of process variations on the critical path delay distribution of 3D ICs
Found in: Quality Electronic Design, International Symposium on
By Siddharth Garg, Diana Marculescu
Issue Date:March 2009
pp. 147-155
3D Integrated Circuits (ICs) have been recently proposed as a solution to the increasing wire delay concerns in scaled technologies. At the same time, technology scaling leads to increasing variability in manufacturing process parameters, making it imperat...
 
System-level throughput analysis for process variation aware multiple voltage-frequency island designs
Found in: ACM Transactions on Design Automation of Electronic Systems (TODAES)
By Diana Marculescu, Siddharth Garg, Siddharth Garg
Issue Date:September 2008
pp. 1-25
The increasing variability in manufacturing process parameters is expected to lead to significant performance degradation in deep submicron technologies. Multiple Voltage-Frequency Island (VFI) design styles with fine-grained, process-variation aware clock...
     
Reliable Computing with Ultra-Reduced Instruction Set Co-processors
Found in: IEEE Micro
By Dan Wang,Aravindkumar Rajendiran,Hiren Patel,Sundaram Ananthanarayanan,Mahesh Tripunitara,Siddharth Garg
Issue Date:December 2013
pp. 1
This work presents a method to reliably perform computations in the presence of hard faults arising from aggressive technology scaling, and design defects from human error. Our method is based on the observation that a single Turing-complete instruction ca...
 
HaDeS: architectural synthesis for <u>h</u>eterogeneous <u>d</u>ark <u>s</u>ilicon chip multi-processors
Found in: Proceedings of the 50th Annual Design Automation Conference (DAC '13)
By Siddharth Garg, Yatish Turakhia
Issue Date:May 2013
pp. 1-7
In this paper, we propose an efficient iterative optimization based approach for architectural synthesis of dark silicon heterogeneous chip multi-processors (CMPs). The goal is to determine the optimal number of cores of each type to provision the CMP with...
     
Technology-driven limits on runtime power management algorithms for multiprocessor systems-on-chip
Found in: ACM Journal on Emerging Technologies in Computing Systems (JETC)
By Diana Marculescu, Radu Marculescu, Siddharth Garg
Issue Date:October 2012
pp. 1-17
Runtime power management is a critical technique for reducing the energy footprint of digital electronic devices and enabling sustainable computing, since it allows electronic devices to dynamically adapt their power and energy consumption to meet performa...
     
On the Impact of Manufacturing Process Variations on the Lifetime of Sensor Networks
Found in: ACM Transactions on Embedded Computing Systems (TECS)
By Diana Marculescu, Siddharth Garg
Issue Date:July 2012
pp. 1-13
The lifetime of individual nodes in a sensor network depends strongly on the leakage power of the nodes in idle state. With technology scaling, variability in leakage power dissipation of sensor nodes will cause increased variability in their lifetimes. In...
     
EmPower: FPGA based emulation of dynamic power management algorithms for multi-core systems on chip (abstract only)
Found in: Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays (FPGA '12)
By Andrew Kennings, Chirag Ravishankar, Sundaram Ananthanarayanan, Siddharth Garg
Issue Date:February 2012
pp. 266-266
Dynamic power management for multi-core system on chip (MPSoC) platforms has become an increasingly critical design problem. In this paper, we present EmPower, an FPGA based emulation, validation and prototyping framework for dynamic power management resea...
     
Custom feedback control: enabling truly scalable on-chip power management for MPSoCs
Found in: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design (ISLPED '10)
By Diana Marculescu, Radu Marculescu, Siddharth Garg
Issue Date:August 2010
pp. 425-430
In this paper, we propose Custom Feedback Control, a new dynamic voltage and frequency control architecture for MP-SoC designs that bridges the gap between the two extreme points on the performance versus implementation cost trade-off curve, i.e., fully-ce...
     
Technology-driven limits on DVFS controllability of multiple voltage-frequency island designs: a system-level perspective
Found in: Proceedings of the 46th Annual Design Automation Conference (DAC '09)
By Diana Marculescu, Radu Marculescu, Siddharth Garg, Umit Ogras
Issue Date:July 2009
pp. 818-821
In this paper, we consider the case of network-on-chip (NoC) based multiple-processor systems-on-chip (MPSoCs) implemented using multiple voltage and frequency islands (VFIs) that rely on fine-grained dynamic voltage and frequency scaling (DVFS) for run-ti...
     
System-level mitigation of WID leakage power variability using body-bias islands
Found in: Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis (CODES/ISSS '08)
By Diana Marculescu, Siddharth Garg
Issue Date:October 2008
pp. 1001-1001
Adaptive Body Biasing (ABB) is a popularly used technique to mitigate the increasing impact of manufacturing process variations on leakage power dissipation. The efficacy of the ABB technique can be improved by partitioning a design into a number of "body-...
     
Interactive presentation: System-level process variation driven throughput analysis for single and multiple voltage-frequency island designs
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '07)
By Diana Marculescu, Siddharth Garg
Issue Date:April 2007
pp. 403-408
Manufacturing process variations are the primary cause of timing yield loss in aggressively scaled technologies. In this paper, we analyze the impact of process variations on the throughput (rate) characteristics of embedded systems comprised of multiple v...
     
System-level process-driven variability analysis for single and multiple voltage-frequency island systems
Found in: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design (ICCAD '06)
By Diana Marculescu, Siddharth Garg
Issue Date:November 2006
pp. 541-546
The problem of determining bounds for application completion times running on generic systems comprised of single or multiple voltage-frequency islands (VFIs) with arbitrary topologies is addressed in the context of manufacturing-driven variability. The ap...
     
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