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Displaying 1-12 out of 12 total
Integrating formal methods tools to support system design
Found in: Engineering of Complex Computer Systems, IEEE International Conference on
By Shiu-Kai Chin, J. Faust, J. Giordano
Issue Date:November 1995
pp. 88
System engineering requires design and verification at several levels of abstraction-from top-level process descriptions down to gate-level hardware designs. A variety of tools such as specification languages, simulators, model checkers, theorem-provers, a...
Formal Development of Secure Email
Found in: Hawaii International Conference on System Sciences
By Dan Zhou, Joncheng C. Kuo, Susan Older, Shiu-Kai Chin
Issue Date:January 1999
pp. 3064
Developing systems that are assured to be secure requires precise and accurate descriptions of specifications, designs, implementations, and security properties. Formal specification and verification have long been recognized as giving the highest degree o...
Experience extending VLSI design with mathematical logic
Found in: Microelectronics Systems Education, IEEE International Conference on/Multimedia Software Engineering, International Symposium on
By Shiu-Kai Chin
Issue Date:July 1997
pp. 0011
Abstract: The growing demands for assurance of properties like correctness, safety, and security have led to the development of design methods using mathematical logic. These methods have broad application to hardware, software, and system design. Design b...
Hardware Composition with Hardware Flowcharts and Process Algebras
Found in: Engineering of Complex Computer Systems, IEEE International Conference on
By Juin-Yeu Joseph Lu, Jang Dae Kim, Shiu-Kai Chin
Issue Date:October 1996
pp. 352
Algorithmic state machine (ASM) descriptions or hardware flowcharts have been used successfully to describe and verify large systems like the IBM 3081. Hardware flowcharts are intuitively appealing in their specification of control flow and data path opera...
Extending VLSI design with higher-order logic
Found in: Computer Design, International Conference on
By A. Chavan, Shiu-Kai Chin, S. Ikram, Jang Dae Kim, Juin-Yeu Zu
Issue Date:October 1995
pp. 85
Extending VLSI CAD with higher-order logic integrates formal verification with synthesis. The benefits of doing so are: 1) relating instruction-set descriptions to implementations, 2) designing at a higher level of abstraction than at the level of schemati...
Engineering Assurance at the Undergraduate Level
Found in: IEEE Security & Privacy
By Susan Older,Shiu-Kai Chin
Issue Date:November 2012
pp. 74-77
What would it take for undergraduate computer engineering and computer science programs to routinely produce graduates who can design computer systems that are assured to operate securely? To help answer that question, Syracuse University piloted the under...
Integrating Security into the Curriculum
Found in: Computer
By Cynthia E. Irvine, Shiu-Kai Chin, Deborah Frincke
Issue Date:December 1998
pp. 25-30
<p>An educational system that cultivates an appropriate knowledge of computer security will increase the likelihood that the next generation of IT workers will have the background needed to design and develop systems that are engineered to be reliabl...
Formal Methods Applied to Secure Network Engineering
Found in: Engineering of Complex Computer Systems, IEEE International Conference on
By Shiu-Kai Chin, John Faust, Joseph Giordano
Issue Date:October 1996
pp. 344
Security properties such as privacy, authentication, and integrity are of increasing importance to networked systems. Systems with security requirements typically must operate with a high degree of confidence, i.e. they must be highly assured. We show how ...
Formal specification and verification of communication protocols using automated tools
Found in: Engineering of Complex Computer Systems, IEEE International Conference on
By M. Barjaktarovic, Shiu-Kai Chin, K. Jabbour
Issue Date:November 1995
pp. 246
The paper compares and contrasts various methods presently available for specification, validation and verification, with emphasis on verification. We describe an application of formal methods to protocol specification, validation, and verification, using ...
Formal Verification of Tree-Structured Carry-Lookahead Adders
Found in: Great Lakes Symposium on VLSI
By Sae Hwan Kim, Shiu-Kai Chin
Issue Date:March 1999
pp. 232
Quad trees { trees with four branches, are used to abstractly describe tree-structured carry-lookahead adders using 4-bit components. The specification and implementation descriptions are parameterized and describe tree-structured adders having arbitrarily...
Formal specification and verification of the kernel functional unit of the OSI session layer protocol and service using CCS
Found in: Proceedings of the 1996 international symposium on Software testing and analysis (ISSTA '96)
By Kamal Jabbour, Milica Barjaktarovic, Shiu-Kai Chin
Issue Date:January 1996
pp. 240
This paper describes an application of formal methods to protocol specification, validation and verification. Formal methods can be incorporated in protocol design and testing so that time and resources are saved on implementation, testing, and documentati...
High-confidence design for security: don't trust---verify
Found in: Communications of the ACM
By Shiu-Kai Chin
Issue Date:January 1988
pp. 33-37
The online Risks Forum has long been a hotbed for discussions of the relative merits of openness relating to the dissemination of knowledge about security vulnerabilities. The debate has now been rekindled, and is summarized here.