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Displaying 1-6 out of 6 total
Integrating formal verification and high-level processor pipeline synthesis
Found in: Application Specific Processors, Symposium on
By Eriko Nurvitadhi,James C. Hoe,Timothy Kam,Shih-Lien L. Lu
Issue Date:June 2011
pp. 22-29
When a processor implementation is synthesized from a specification using an automatic framework, this implementation still should be verified against its specification to ensure the automatic framework introduced no error. This paper presents our effort i...
Content Addressable Memory for Low-Power and High-Performance Applications
Found in: Computer Science and Information Engineering, World Congress on
By Ataur R. Patwary, Bibiche M. Geuskens, Shih-Lien L. Lu
Issue Date:April 2009
pp. 423-427
A low-power 11-transistor Content Addressable Memory (CAM) cell is presented for high performance applications. The CAM cell design is based on the conventional 8-transistor one-read and one-write Register File (RF) cell, where a read operation does not af...
Resilient microprocessor design for high performance & energy efficiency
Found in: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design (ISLPED '10)
By Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris B. Wilkerson, James W. Tschanz, Keith A. Bowman, Muhammad M. Khellah, Paolo A. Aseron, Shih-Lien L. Lu, Tanay Karnik, Vivek K. De
Issue Date:August 2010
pp. 355-356
Conventional microprocessors require a clock frequency (FCLK) guardband to ensure correct functionality during infrequent dynamic operating variations in supply voltage (VCC), temperature, and transistor aging. Consequently, these inflexible designs cannot...
Automatic multithreaded pipeline synthesis from transactional datapath specifications
Found in: Proceedings of the 47th Design Automation Conference (DAC '10)
By Eriko Nurvitadhi, James C. Hoe, Shih-Lien L. Lu, Timothy Kam
Issue Date:June 2010
pp. 314-319
We present a technique to automatically synthesize a multithreaded in-order pipeline from a high-level unpipelined datapath specification. This work extends the previously proposed transactional specification (T-spec) and synthesis technology (T-piper). Th...
An FPGA-based Pentium® in a complete desktop system
Found in: Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays (FPGA '07)
By Michael Konow, Peter Yiannacouras, Rolf Kassa, Shih-Lien L. Lu, Taeweon Suh
Issue Date:February 2007
pp. 53-59
Software simulation has been the predominant method for architects to evaluate microprocessor research proposals. There are three tenets in modeling new designs with software models: simulation speed, model accuracy and model completeness. The increasing c...
Design, implementation, and verification of active cache emulator (ACE)
Found in: Proceedings of the internation symposium on Field programmable gate arrays (FPGA'06)
By Eriko Nurvitadhi, Jumnit Hong, Shih-Lien L. Lu
Issue Date:February 2006
pp. 63-72
This paper presents the design, implementation, and verification of the Active Cache Emulator (ACE), a novel FPGA-based emulator that models an L3 cache actively and in real-time. ACE leverages interactions with its host system to model the target system (...