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Displaying 1-8 out of 8 total
3D Integration for Introspection
Found in: IEEE Micro
By Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood
Issue Date:January 2007
pp. 77-83
In today's complex processors, specialized profiling and introspection hardware would be incredibly beneficial to software developers, but most proposals for its addition would increase the cost of every die manufactured. Modular,
 
A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs
Found in: Computer Design, International Conference on
By Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee
Issue Date:October 2005
pp. 411-416
<p>As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for VLSI design. This paper, for the first time, proposes a systematic methodology to determine ...
 
Simultaneous Optimization of Supply and Threshold Voltages for Low-Power and High-Performance Circuits in the Leakage Dominant Era
Found in: Design Automation Conference
By Anirban Basu, Sheng-Chih Lin, Vineet Wason, Amit Mehrotra, Kaustav Banerjee
Issue Date:June 2004
pp. 884-887
Electrothermal couplings between supply voltage, operating frequency, power dissipation and die temperature have been shown to significantly impact the energy-delay-product (EDP) based simultaneous optimization of supply (V{dd}) and threshold (V{th}) volta...
 
A Comprehensive Analytical Capacitance Model of a Two Dimensional Nanodot Array
Found in: Quality Electronic Design, International Symposium on
By Anirban Basu, Sheng-Chih Lin, Christoph Wasshuber, Adrian M. Ionescu, Kaustav Banerjee
Issue Date:March 2004
pp. 259-264
This paper introduces a new comprehensive analytical capacitance model for nanoscale architectures based on nanoscale metallic/semiconducting dots. The model takes into account a detailed charge interaction of the components and shows their implications on...
 
An electrothermally-aware full-chip substrate temperature gradient evaluation methodology for leakage dominant technologies with implications for power estimation and hot-spot management
Found in: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design (ICCAD '06)
By Kaustav Banerjee, Sheng-Chih Lin
Issue Date:November 2006
pp. 568-574
As CMOS technology scales into the nanometer regime, power dissipation and associated thermal concerns in high-performance ICs due to on-chip hot-spots and thermal gradients are beginning to impact VLSI design. Moreover, elevated substrate (junction or die...
     
Introspective 3D chips
Found in: Proceedings of the 12th international conference on Architectural support for programming languages and operating systems (ASPLOS-XII)
By Banit Agrawal, Kaustav Banerjee, Navin Srivastava, Shashidhar Mysore, Sheng-Chih Lin, Tim Sherwood
Issue Date:October 2006
pp. 109-es
While the number of transistors on a chip increases exponentially over time, the productivity that can be realized from these systems has not kept pace. To deal with the complexity of modern systems, software developers are increasingly dependent on specia...
     
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Found in: Proceedings of the 43rd annual conference on Design automation (DAC '06)
By Banit Agrawal, Gian Luca Loi, Kaustav Banerjee, Navin Srivastava, Sheng-Chih Lin, Timothy Sherwood
Issue Date:July 2006
pp. 991-996
Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several other advantages, it is expected that the benefits from this technology can poten...
     
Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems
Found in: Proceedings of the 2006 conference on Asia South Pacific design automation (ASP-DAC '06)
By Kaustav Banerjee, Navin Srivastava, Sheng-Chih Lin
Issue Date:January 2006
pp. 223-230
Management of electrothermal (ET) issues arising due to power dissipation both at the micro- and macro- scale is central to the development of future generation microprocessors, integrated networks, and other highly integrated circuits and systems. This pa...
     
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