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Displaying 1-11 out of 11 total
Gate-Level Information-Flow Tracking for Secure Architectures
Found in: IEEE Micro
By Mohit Tiwari, Xun Li, Hassan M.G. Wassel, Bita Mazloom, Shashidhar Mysore, Frederic T. Chong, Timothy Sherwood
Issue Date:January 2010
pp. 92-100
<p>This article describes a new method for constructing and analyzing architectures that can track all information flows within a processor, including explicit, implicit, and timing flows. The key to this approach is a novel gate-level information-fl...
 
Quantifying the Potential of Program Analysis Peripherals
Found in: Parallel Architectures and Compilation Techniques, International Conference on
By Mohit Tiwari, Shashidhar Mysore, Timothy Sherwood
Issue Date:September 2009
pp. 53-63
Tools such as multi-threaded data race detectors, memory bounds checkers, dynamic type analyzers, data flight recorders, and various performance profilers are becoming increasingly vital aids to software developers. Rather than performing all the instrumen...
 
A small cache of large ranges: Hardware methods for efficiently searching, storing, and updating big dataflow tags
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Mohit Tiwari, Banit Agrawal, Shashidhar Mysore, Jonathan Valamehr, Timothy Sherwood
Issue Date:November 2008
pp. 94-105
Dynamically tracking the flow of data within a microprocessor creates many new opportunities to detect and track malicious or erroneous behavior, but these schemes all rely on the ability to associate tags with all of virtual or physical memory. If one wis...
 
Exploring the Processor and ISA Design for Wireless Sensor Network Applications
Found in: VLSI Design, International Conference on
By Shashidhar Mysore, Banit Agrawal, Frederic T. Chong, Timothy Sherwood
Issue Date:January 2008
pp. 59-64
Power consumption, physical size, and architecture de- sign of sensor node processors have been the focus of sen- sor network research in the architecture community. What lies at the foundation for these research is the hardware- level design which determi...
 
3D Integration for Introspection
Found in: IEEE Micro
By Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood
Issue Date:January 2007
pp. 77-83
In today's complex processors, specialized profiling and introspection hardware would be incredibly beneficial to software developers, but most proposals for its addition would increase the cost of every die manufactured. Modular,
 
Profiling over Adaptive Ranges
Found in: Code Generation and Optimization, IEEE/ACM International Symposium on
By Shashidhar Mysore, Banit Agrawal, Timothy Sherwood, Nisheeth Shrivastava, Subhash Suri
Issue Date:March 2006
pp. 147-158
<p>Modern computer systems are called on to deal with billions of events every second, whether they are instructions executed, memory locations accessed, or packets forwarded. This presents a serious challenge to those who seek to quantify, analyze, ...
 
Formulating and implementing profiling over adaptive ranges
Found in: ACM Transactions on Architecture and Code Optimization (TACO)
By Banit Agrawal, Nisheeth Shrivastava, Nisheeth Shrivastava, Rodolfo Neuber, Rodolfo Neuber, Shashidhar Mysore, Shashidhar Mysore, Subhash Suri, Subhash Suri, Timothy Sherwood, Timothy Sherwood
Issue Date:May 2008
pp. 1-32
Modern computer systems are called on to deal with billions of events every second, whether they are executed instructions, accessed memory locations, or forwarded packets. This presents a serious challenge to those who seek to quantify, analyze, or optimi...
     
Dataflow Tomography: Information Flow Tracking For Understanding and Visualizing Full Systems
Found in: ACM Transactions on Architecture and Code Optimization (TACO)
By Bita Mazloom, Shashidhar Mysore, Tim Sherwood, Banit Agrawal, Mohit Tiwari
Issue Date:March 2012
pp. 1-26
It is not uncommon for modern systems to be composed of a variety of interacting services, running across multiple machines in such a way that most developers do not really understand the whole system. As abstraction is layered atop abstraction, developers...
     
Complete information flow tracking from the gates up
Found in: Proceeding of the 14th international conference on Architectural support for programming languages and operating systems (ASPLOS '09)
By Bita Mazloom, Frederic T. Chong, Hassan M.G. Wassel, Mohit Tiwari, Shashidhar Mysore, Timothy Sherwood
Issue Date:March 2009
pp. 23-27
For many mission-critical tasks, tight guarantees on the flow of information are desirable, for example, when handling important cryptographic keys or sensitive financial data. We present a novel architecture capable of tracking all information flow within...
     
Understanding and visualizing full systems with data flow tomography
Found in: Proceedings of the 13th international conference on Architectural support for programming languages and operating systems (ASPLOS XIII)
By Banit Agrawal, Bita Mazloom, Shashidhar Mysore, Timothy Sherwood
Issue Date:March 2008
pp. 1-1
It is not uncommon for modern systems to be composed of a variety of interacting services, running across multiple machines in such a way that most developers do not really understand the whole system. As abstraction is layered atop abstraction, developers...
     
Introspective 3D chips
Found in: Proceedings of the 12th international conference on Architectural support for programming languages and operating systems (ASPLOS-XII)
By Banit Agrawal, Kaustav Banerjee, Navin Srivastava, Shashidhar Mysore, Sheng-Chih Lin, Tim Sherwood
Issue Date:October 2006
pp. 109-es
While the number of transistors on a chip increases exponentially over time, the productivity that can be realized from these systems has not kept pace. To deal with the complexity of modern systems, software developers are increasingly dependent on specia...
     
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