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Displaying 1-45 out of 45 total
A fast and accurate multi-cycle soft error rate estimation approach to resilient embedded systems design
Found in: Dependable Systems and Networks, International Conference on
By Mahdi Fazeli, Seyed Ghassem Miremadi, Hossein Asadi, Seyed Nematollah Ahmadian
Issue Date:July 2010
pp. 131-140
In this paper, we propose a very fast and accurate analytical approach to estimate the overall SER and to identify the most vulnerable gates, flip-flops, and paths of a circuit. Using such information, designers can selectively protect the vulnerable parts...
 
A Low Power Error Detection Technique for Floating-Point Units in Embedded Applications
Found in: Embedded and Ubiquitous Computing, IEEE/IFIP International Conference on
By Seyed Mohammad Hossein Shekarian, Alireza Ejlali, Seyed Ghassem Miremadi
Issue Date:December 2008
pp. 199-205
Reliability and low power consumption are two major design objectives in today's embedded systems. Since floating-point units (FPU) are required for some embedded applications (e.g., multimedia applications), careful considerations should be given to the r...
 
A Software-Based Error Detection Technique Using Encoded Signatures
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Yasser Sedaghat, Seyed Ghassem Miremadi, Mahdi Fazeli
Issue Date:October 2006
pp. 389-400
In this Paper, a software-based control flow checking technique called SWTES (Softwarebased error detection Technique using Encoded Signatures) is presented and evaluated. This technique is processor independent and can be applied to any kind of processors...
 
FTSPM: A Fault-Tolerant ScratchPad Memory
Found in: 2013 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)
By Amir Mahdi Hosseini Monazzah,Hamed Farbeh,Seyed Ghassem Miremadi,Mahdi Fazeli,Hossein Asadi
Issue Date:June 2013
pp. 1-10
ScratchPad Memory (SPM) is an important part of most modern embedded processors. The use of embedded processors in safety-critical applications implies including fault tolerance in the design of SPM. This paper proposes a method, called FTSPM, which integr...
 
Memory Mapped SPM: Protecting Instruction Scratchpad Memory in Embedded Systems against Soft Errors
Found in: European Dependable Computing Conference
By Hamed Farbeh,Mahdi Fazeli,Faramarz Khosravi,Seyed Ghassem Miremadi
Issue Date:May 2012
pp. 218-226
Predictability, energy consumption, area and reliability are the major concerns in embedded systems. Using scratchpad memories (SPMs) instead of cache memories play an increasing role to satisfy these concerns. Both cache and SPM as on-chip SRAM memories a...
 
Low Cost Concurrent Error Detection for On-Chip Memory Based Embedded Processors
Found in: Embedded and Ubiquitous Computing, IEEE/IFIP International Conference on
By Faramarz Khosravi,Hamed Farbeh,Mahdi Fazeli,Seyed Ghassem Miremadi
Issue Date:October 2011
pp. 114-119
This paper proposes an efficient concurrent error detection method using control flow checking for embedded processors. The proposed method is based on the co-operation of two hardware modules: 1) an on-chip hardware component to detect branch instructions...
 
Numeral-Based Crosstalk Avoidance Coding to Reliable NoC Design
Found in: Digital Systems Design, Euromicro Symposium on
By Mansour Shafaei,Ahmad Patooghy,Seyed Ghassem Miremadi
Issue Date:September 2011
pp. 55-62
This paper proposes a Numeral-Based Crosstalk Avoidance Coding (NB-CAC) to protect communication channels of Network-on-Chips (NoCs) against crosstalk faults. The NB-CAC scheme produces code words without bit patterns '101' and '010' to eliminate harmful t...
 
A Fast Analytical Approach to Multi-cycle Soft Error Rate Estimation of Sequential Circuits
Found in: Digital Systems Design, Euromicro Symposium on
By Mahdi Fazeli, Seyed Ghassem Miremadi, Hossein Asadi, Mehdi Baradaran Tahoori
Issue Date:September 2010
pp. 797-800
In this paper, we propose a very fast analytical approach to measure the overall circuit Soft Error Rate (SER) and to identify the most vulnerable gates and flip-flops. In the proposed approach, we first compute the error propagation probability from an er...
 
An Efficient Method to Reliable Data Transmission in Network-on-Chips
Found in: Digital Systems Design, Euromicro Symposium on
By Ahmad Patooghy, Hamed Tabkhi, Seyed Ghassem Miremadi
Issue Date:September 2010
pp. 467-474
Data transmission in Network-on-Chips (NoCs) is a serious problem due to cross talk faults happening in adjacent communication links. This paper proposes an efficient flow-control method to enhance the reliability of packet transmission in Network-on-Chips...
 
Performability Comparison of Schedulability Conditions in Real-Time Embedded Systems
Found in: Dependability, International Conference on
By Mohsen Bashiri, Seyed Ghassem Miremadi
Issue Date:July 2010
pp. 70-75
In modern safety-critical real-time embedded systems, performance and reliability are two most important parameters. The joint consideration of these two parameters is called performability. This paper evaluates and compares different schedulability condit...
 
RMAP: A Reliability-Aware Application Mapping for Network-on-Chips
Found in: Dependability, International Conference on
By Ahmad Patooghy, Hamed Tabkhi, Seyed Ghassem Miremadi
Issue Date:July 2010
pp. 112-117
This paper proposes a reliability-aware application mapping for mesh-based NoCs. The proposed reliable mapping, called RMAP, adds redundant communications to the application graph in order to improve the reliability of packet delivery in NoCs. The RMAP div...
 
Feature Specific Control Flow Checking in COTS-Based Embedded Systems
Found in: Dependability, International Conference on
By Amir Rajabzadeh, Seyed Ghassem Miremadi
Issue Date:July 2010
pp. 58-63
While the Control Flow Checking (CFC) methods are using the ordinary instruction set and general Arithmetic and Logic Unit (ALU) features to protect the programs against the transient faults, this paper presents a new kind of CFC method, called feature spe...
 
Investigating the Effects of Schedulability Conditions on the Power Efficiency of Task Scheduling in an Embedded System
Found in: Object-Oriented Real-Time Distributed Computing, IEEE International Symposium on
By Mohsen Bashiri, Seyed Ghassem Miremadi
Issue Date:May 2010
pp. 102-106
Power consumption, performance and reliability are the most important parameters in modern safety-critical distributed real-time embedded systems. This paper evaluates and compares different schedulability conditions in fault-tolerant Rate-Monotonic (RM) a...
 
Reliability & Performance Modeling to Speed-Up the NoC Design
Found in: Pacific Rim International Symposium on Dependable Computing, IEEE
By Ahmad Patooghy,Seyed Ghassem Miremadi
Issue Date:November 2009
pp. 208-213
Flow-control methods are effective ways to enhance the reliability of Network-on-Chips against transients occurring in deep sub-micron chips. This paper proposes an analytical model to predict the reliability and performance of mesh-based NoCs equipped wit...
 
A Low-Cost On-Line Monitoring Mechanism for the FlexRay Communication Protocol
Found in: Dependable Computing, Latin-American Symposium on
By Yasser Sedaghat, Seyed Ghassem Miremadi
Issue Date:September 2009
pp. 111-118
Nowadays, communication protocols are used in safety-critical automotive applications. In these applications, fault tolerance is a main requirement and the existence of single points of failure is a serious threat to system failures. Among the communicatio...
 
A low-cost fault-tolerant technique for Carry Look-Ahead adder
Found in: On-Line Testing Symposium, IEEE International
By Alireza Namazi, Yasser Sedaghat, Seyed Ghassem Miremadi, Alireza Ejlali
Issue Date:June 2009
pp. 217-222
This paper proposes a low-cost fault-tolerant Carry Look-Ahead (CLA) adder which consumes much less power and area overheads in comparison with other fault-tolerant CLA adders. Analytical and experimental results show that this adder corrects all single-bi...
 
Categorizing and Analysis of Activated Faults in the FlexRay Communication Controller Registers
Found in: European Test Symposium, IEEE
By Yasser Sedaghat, Seyed Ghassem Miremadi
Issue Date:May 2009
pp. 121-126
FlexRay communication protocol is expected becoming the de-facto standard for distributed safety-critical systems. In this paper, transient single bit-flip faults were injected into the FlexRay communication controller to categorize and analyze the activat...
 
Fault Tolerant and Low Energy Write-Back Heterogeneous Set Associative Cache for DSM Technologies
Found in: Availability, Reliability and Security, International Conference on
By Mehrtash Manoochehri, Alireza Ejlali, Seyed Ghassem Miremadi
Issue Date:March 2009
pp. 448-453
This paper presents a fault tolerant and energy efficient write-back set-associative cache, which has a heterogeneous structure. The cache architecture is based on partitioning the ways of each set into two different parts. In each set, one cache way uses ...
 
A High Speed and Low Cost Error Correction Technique for the Carry Select Adder
Found in: Availability, Reliability and Security, International Conference on
By Alireza Namazi, Seyed Ghassem Miremadi, Alireza Ejlali
Issue Date:March 2009
pp. 635-640
In this paper, a high speed and low cost error correction technique is proposed for the Carry Select Adder (CSA) which can correct both transient and permanent errors and is applicable on all partitioning types of the basic CSA circuit. The proposed error ...
 
A Micro-FT-UART for Safety-Critical SoC-Based Applications
Found in: Availability, Reliability and Security, International Conference on
By Mohammad-Hamed Razmkhah, Seyed Ghassem Miremadi, Alireza Ejlali
Issue Date:March 2009
pp. 316-321
This paper presents the design of a fault-tolerant universal asynchronous receiver transmitter (UART) called micro-FT-UART for safety-critical SoC-based applications. This UART exploits advantages of three fault-tolerant techniques to tolerate soft errors....
 
Joint write policy and fault-tolerance mechanism selection for caches in DSM technologies: Energy-reliability trade-off
Found in: Quality Electronic Design, International Symposium on
By Mehrtash Manoochehri, Alireza Ejlali, Seyed Ghassem Miremadi
Issue Date:March 2009
pp. 839-844
Write-through caches potentially have higher reliability than write-back caches. However, write-back caches are more energy efficient. This paper provides a comparison between the write-back and write-through policies based on the combination of reliabilit...
 
XYX: A Power & Performance Efficient Fault-Tolerant Routing Algorithm for Network on Chip
Found in: Parallel, Distributed, and Network-Based Processing, Euromicro Conference on
By Ahmad Patooghy, Seyed Ghassem Miremadi
Issue Date:February 2009
pp. 245-251
Reliability is one of the main concerns in the design of network on chips due to the use of deep-sub micron technologies in fabrication of such products. This paper proposes a fault-tolerant routing algorithm called XYX which is based on sending redundant ...
 
Control-Flow Checking Using Branch Instructions
Found in: Embedded and Ubiquitous Computing, IEEE/IFIP International Conference on
By Mostafa Jafari-Nodoushan, Seyed Ghassem Miremadi, Alireza Ejlali
Issue Date:December 2008
pp. 66-72
This paper presents a hardware control-flow checking scheme for RISC processor-based systems. This Scheme combines two error detection mechanisms to provide high coverage. The first mechanism uses parity bits to detect faults occurring in the opcodes and i...
 
An Asymmetric Checkpointing and Rollback Error Recovery Scheme for Embedded Processors
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Hamed Tabkhi, Seyed Ghassem Miremadi, Alireza Ejlali
Issue Date:October 2008
pp. 445-453
This paper presents a checkpointing scheme for rollback error recovery, called Asymmetric Checkpointing and Rollback Recovery (ACRR) which stores the processor states in an asymmetric manner. In this way, error recovery latency and the number of checkpoint...
 
FPGA-Based Fault Injection into Synthesizable Verilog HDL Models
Found in: Secure System Integration and Reliability Improvement
By Mohammad Shokrolah-Shirazi, Seyed Ghassem Miremadi
Issue Date:July 2008
pp. 143-149
This paper presents an FPGA-based fault injection tool, called FITO that supports several synthesizable fault models for dependability analysis of digital systems modeled by Verilog HDL. Using the FITO, experiments can be performed in real-time with good c...
 
Analyzing fault effects in the 32-bit OpenRISC 1200 microprocessor
Found in: Availability, Reliability and Security, International Conference on
By Nima Mehdizadeh, Mohammad Shokrolah-Shirazi, Seyed Ghassem Miremadi
Issue Date:March 2008
pp. 648-652
This paper presents an analysis of the effects and propagation of faults in the open-core 32-bit OpenRISC 1200 microprocessor. The analysis is based on a total of 13,000 transient faults injected into 65 parts of the CPU module in the OpenRISC 1200 core de...
 
Fault Effects in FlexRay-Based Networks with Hybrid Topology
Found in: Availability, Reliability and Security, International Conference on
By Mehdi Dehbashi, Vahid Lari, Seyed Ghassem Miremadi, Mohammad Shokrollah-Shirazi
Issue Date:March 2008
pp. 491-496
This paper investigates fault effects and error propagation in a FlexRay-based network with hybrid topology that includes a bus subnetwork and a star subnetwork. The investigation is based on about 43500 bit-flip fault injection inside different parts of t...
 
A Power Efficient Approach to Fault-Tolerant Register File Design
Found in: VLSI Design, International Conference on
By Mojtaba Amiri-Kamalabad, Seyed Ghassem Miremadi, Mahdi Fazeli
Issue Date:January 2008
pp. 21-26
Recently, the trade-off between power consumption and fault tolerance in embedded processors has been highlighted. This paper proposes an approach to reduce dynamic power of conventional high-level fault- tolerant techniques used in the register file of pr...
 
Improving Network's Performability Using Parallel Processing
Found in: International Conference on Networking
By Mostafa Shaad Zolpirani, Mohammad-Mahdi Bidmeshki, Seyed Ghassem Miremadi
Issue Date:April 2007
pp. 40
By occurring failures in computer networks, routing protocols are triggered to update routing and forwarding tables. Because of invalid tables during update-time, transient loop may occur and packet-drop rate and end-to-end delay increase which means that ...
 
Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs
Found in: Parallel and Distributed Processing Symposium, International
By Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan
Issue Date:March 2007
pp. 188
FPGAs are an appealing solution for the space-based remote sensing applications. However, in a low-earth orbit, configuration bits of SRAM-based FPGAs are susceptible to single-event upsets (SEUs). In this paper, a new protected CLB and FPGA architecture a...
 
Fault-Tolerant Earliest-Deadline-First Scheduling Algorithm
Found in: Parallel and Distributed Processing Symposium, International
By Hakem Beitollahi, Seyed Ghassem Miremadi, Geert Deconinck
Issue Date:March 2007
pp. 418
The general approach to fault tolerance in uniprocessor systems is to maintain enough time redundancy in the schedule so that any task instance can be re-executed in presence offaults during the execution. In this paper a scheme is presented to add enough ...
 
Contribution of Controller Area Networks Controllers to Masquerade Failures
Found in: Pacific Rim International Symposium on Dependable Computing, IEEE
By Hassan Salmani, Seyed Ghassem Miremadi
Issue Date:December 2005
pp. 310-316
This paper scrutinizes faults in a CAN controller that may result in masquerade failures, and suggests an even parity mechanism to detect them with minimum hardware overhead. To do this, a CAN controller is modeled by VHDL at behavioral level and is exploi...
 
A Hardware Approach to Concurrent Error Detection Capability Enhancement in COTS Processors
Found in: Pacific Rim International Symposium on Dependable Computing, IEEE
By Amir Rajabzadeh, Seyed Ghassem Miremadi
Issue Date:December 2005
pp. 83-90
To enhance the error detection capability in COTS (commercial off-the-shelf) -based design of safetycritical systems, a new hardware-based control flow checking (CFC) technique will be presented. This technique, Control Flow Checking by Execution Tracing (...
 
Investigation of Transient Effects on FPGA-based Embedded Systems
Found in: Embedded Software and Systems, Second International Conference on
By Ali Bakhoda, Seyed Ghassem Miremadi, Hamid R. Zarandi
Issue Date:December 2005
pp. 231-236
In this paper, we present an experimental evaluation of transient effects on an embedded system which uses SRAM-based FPGAs. A total of 7500 transient faults were injected into the target FPGA using Power Supply Disturbances (PSD) and a simple 8-bit microp...
 
A Software-Based Concurrent Error Detection Technique for PowerPC Processor-based Embedded Systems
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Mahdi Fazeli, Reza Farivar, Seyed Ghassem Miremadi
Issue Date:October 2005
pp. 266-274
<p>This paper presents a behavior-based error detection technique called Control Flow Checking using Branch Trace Exceptions for PowerPC processors family (CFCBTE). This technique is based on the branch trace exception feature available in the PowerP...
 
Hierarchical Multiple Associative Mapping in Cache Memories
Found in: Engineering of Computer-Based Systems, IEEE International Conference on the
By Hamid R. Zarandi, Seyed Ghassem Miremadi
Issue Date:April 2005
pp. 95-101
In this paper, a new cache placement scheme is proposed to achieve higher hit ratios with respect to the two conventional schemes namely set-associative and direct mapping. Similar to set-associative, in this scheme, cache space is divided into sets of dif...
 
Fault Detection Enhancement in Cache Memories Using a High Performance Placement Algorithm
Found in: On-Line Testing Symposium, IEEE International
By Hamid R. Zarandi, Seyed Ghassem Miremadi, Hamid Sarbazi-Azad
Issue Date:July 2004
pp. 101
Data integrity of words coming out of the caches needs to be checked to assure their correctness. This paper proposes a cache placement scheme, which provides high performance as well as high fault detection coverage. In this scheme, the cache space is div...
 
Experimental Evaluation of Master/Checker Architecture Using Power Supply- and Software-Based Fault Injection
Found in: On-Line Testing Symposium, IEEE International
By Amir Rajabzadeh, Seyed Ghassem Miremadi, Mirzad Mohandespour
Issue Date:July 2004
pp. 239
This paper presents an experimental evaluation of the effectiveness of the Master/Checker (M/C) architecture in a 32-bit Pentium processor system using both power-supply disturbance (PSD) fault injection and software-implemented fault injection (SWIFI) met...
 
Evaluation of Fault-Tolerant Designs Implemented on SRAM-Based FPGAs
Found in: Pacific Rim International Symposium on Dependable Computing, IEEE
By Ghazanfar Asadi, Seyed Ghassem Miremadi, Hamid R. Zarandi, Alireza Ejlali
Issue Date:March 2004
pp. 327-332
The technology of SRAM-based devices is sensible to Single Event Upsets (SEUs) that may be induced mainly by high energy heavy ions and neutrons. This paper presents a framework for the evaluation of fault-tolerant designs implemented on SRAM-based FPGAs u...
 
Fault Injection into Verilog Models for Dependability Evaluation of Digital Systems
Found in: Parallel and Distributed Computing, International Symposium on
By Hamid R. Zarandi, Seyed Ghassem Miremadi, Alireza Ejlali
Issue Date:October 2003
pp. 281
This paper presents transient and permanent fault injection into Verilog models of digital systems during the design phase by a developed simulation-based fault injection tool called INJECT. With this fault injection tool, it is possible to inject crucial ...
 
A Hybrid Fault Injection Approach Based on Simulation and Emulation Co-operation
Found in: Dependable Systems and Networks, International Conference on
By Alireza Ejlali, Seyed Ghassem Miremadi, Hamidreza Zarandi, Ghazanfar Asadi, Siavash Bayat Sarmadi
Issue Date:June 2003
pp. 479
This paper presents a new fault injection approach, which is based on a co-operation between a simulator and an emulator. This hybrid approach utilizes the advantages of both simulation-based fault injection as well as physical fault injection to provide a...
 
Switch-Level Emulation
Found in: Design Automation Conference
By Alireza Ejlali, Seyed Ghassem Miremadi
Issue Date:June 2003
pp. 644
This paper presents a method for the fast emulation of switch-level circuits using FPGAs. In this method, logic gates are used to model switch-level circuits without any abstraction. In contrast to the abstraction methods for which transistors are grouped ...
 
A Power Efficient Masking Technique for Design of Robust Embedded Systems against SEUs and SETs
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Mahdi Fazeli, Seyed Ghassem Miremadi
Issue Date:October 2008
pp. 193-201
In this paper, an SET and SEU tolerant latch suitable for use in embedded systems called SETUR (Single Event Transient and Upset Robust latch) is presented and evaluated. The SETUR is based on the use of a redundant feedback line and a CMOS delay element t...
 
Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Hamid R. Zarandi, Seyed Ghassem Miremadi, Alireza Ejlali
Issue Date:November 2003
pp. 485
This paper presents a fault injection tool, called SINJECT that supports several synthesizable and non-synthesizable fault models for dependability analysis of digital systems modeled by popular HDLs. The tool provides injection of transient and permanent ...
 
Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '07)
By Alireza Ejlali, Bashir M. Al-Hashimi, Paul Rosinger, Seyed Ghassem Miremadi
Issue Date:April 2007
pp. 1647-1652
High reliability against noise, low energy consumption and high performance are key objectives in the design of on-chip networks. Recently some researchers have considered the various trade-offs between two of these objectives. However, as we will argue la...
     
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