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Displaying 1-12 out of 12 total
Hardware Trojan Detection by Multiple-Parameter Side-Channel Analysis
Found in: IEEE Transactions on Computers
By Seetharam Narasimhan,Dongdong Du,Rajat Subhra Chakraborty,Somnath Paul,Francis G. Wolff,Christos A. Papachristou,Kaushik Roy,Swarup Bhunia
Issue Date:November 2013
pp. 2183-2195
Hardware Trojan attack in the form of malicious modification of a design has emerged as a major security threat. Side-channel analysis has been investigated as an alternative to conventional logic testing to detect the presence of hardware Trojans. However...
 
Improving IC Security Against Trojan Attacks Through Integration of Security Monitors
Found in: IEEE Design & Test of Computers
By Seetharam Narasimhan,Wen Yueh,Xinmu Wang,Saibal Mukhopadhyay,Swarup Bhunia
Issue Date:October 2012
pp. 37-46
Editor's notes:
 
SCARE: Side-Channel Analysis Based Reverse Engineering for Post-Silicon Validation
Found in: VLSI Design, International Conference on
By Xinmu Wang,Seetharam Narasimhan,Aswin Krishna,Swarup Bhunia
Issue Date:January 2012
pp. 304-309
Reverse Engineering (RE) has been historically considered as a powerful approach to understand electronic hardware in order to gain competitive intelligence or accomplish piracy. In recent years, it has also been looked at as a way to authenticate hardware...
 
Sequential hardware Trojan: Side-channel aware design and placement
Found in: Computer Design, International Conference on
By Xinmu Wang,Seetharam Narasimhan,Aswin Krishna,Tatini Mal-Sarkar,Swarup Bhunia
Issue Date:October 2011
pp. 297-300
Various design-for-security (DFS) approaches have been proposed earlier for detection of hardware Trojans, which are malicious insertions in Integrated Circuits (ICs). In this paper, we highlight our major findings in terms of innovative Trojan design that...
 
NEMTronics: Symbiotic integration of nanoelectronic and nanomechanical devices for energy-efficient adaptive computing
Found in: Nanoscale Architectures, IEEE International Symposium on
By Xinmu Wang,Seetharam Narasimhan,Somnath Paul,Swarup Bhunia
Issue Date:June 2011
pp. 210-217
Heterogeneity, programmability and parallelism are expected to be the key drivers for future nanoelectronics systems. The proposed work builds on these key drivers to achieve an energy-efficient, adaptive, and reliable computing framework. The primary inte...
 
Hardware IP Protection During Evaluation Using Embedded Sequential Trojan
Found in: IEEE Design and Test of Computers
By Seetharam Narasimhan,Rajat Chakraborty,Swarup Bhunia
Publication Date: June 2011
pp. N/A
Evaluation of hardware Intellectual Property (IP) cores is an important step in an IP-based system-on-chip (SoC) design flow. From the perspective of both IP vendors and Integrated Circuit (IC) designers, it is desirable that hardware IPs can be freely eva...
 
VaROT: Methodology for Variation-Tolerant DSP Hardware Design Using Post-Silicon Truncation of Operand Width
Found in: VLSI Design, International Conference on
By Keerthi Kunaparaju, Seetharam Narasimhan, Swarup Bhunia
Issue Date:January 2011
pp. 310-315
With increasing parameter variations in nanoscale technologies, computational blocks in Digital Signal Processing (DSP) hardware become increasingly vulnerable to variation-induced delay failures. These failures can significantly affect the Quality of Serv...
 
A supply-demand model based scalable energy management system for improved energy utilization efficiency
Found in: International Conference on Green Computing
By Seetharam Narasimhan, David McIntyre, Francis Wolff, Yu Zhou, D. Weyer, Swarup Bhunia
Issue Date:August 2010
pp. 97-105
Harvesting energy from the environment can play an important role in reducing the dependency of an electronic system to primary energy sources (i.e. AC power or battery). For reliable and efficient energy harvesting while assuring best user experience, it ...
 
Software exploitable hardware Trojans in embedded processor
Found in: 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
By Xinmu Wang,Tatini Mal-Sarkar,Aswin Krishna,Seetharam Narasimhan,Swarup Bhunia
Issue Date:October 2012
pp. 55-58
Growing threat of hardware Trojan attacks in untrusted foundry or design house has motivated researchers around the world to analyze the threat and develop effective countermeasures. In this paper, we focus on analyzing a specific class of hardware Trojans...
 
On-die CMOS voltage droop detection and dynamiccompensation
Found in: Proceedings of the 18th ACM Great Lakes symposium on VLSI (GLSVLSI '08)
By Matthew Seetharam A. Holtz, Seetharam Narasimhan, Swarup Bhunia
Issue Date:May 2008
pp. 1-37
This paper describes an on-die di/dt voltage droop compensation scheme for use in high current, low voltage, VLSI circuits using current injection. The circuit was designed and simulated with SPICE. The circuit is able to source up to 150mA of current into...
     
Role of power grid in side channel attack and power-grid-aware secure design
Found in: Proceedings of the 50th Annual Design Automation Conference (DAC '13)
By Saibal Mukhopadhyay, Seetharam Narasimhan, Swarup Bhunia, Wen Yueh
Issue Date:May 2013
pp. 1-9
Side-channel attack (SCA) is a method in which an attacker aims at extracting secret information from crypto chips by analyzing physical parameters (e.g. power). SCA has emerged as a serious threat to many mathematically unbreakable cryptography systems. F...
     
Collective computing based on swarm intelligence
Found in: Proceedings of the 45th annual conference on Design automation (DAC '08)
By Seetharam Narasimhan, Somnath Paul, Swarup Bhunia
Issue Date:June 2008
pp. 1-30
We present a novel computing framework consisting of multiple processing cores that exhibits swarm-like behavior. Conventional parallel processing paradigm typically requires a central controller for job assignment, inter-core communications and defect-tol...
     
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