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xMAS: Quick Formal Modeling of Communication Fabrics to Enable Verification
Found in: IEEE Design and Test of Computers
By Satrajit Chatterjee,Mike Kishinevsky,Umit Ogras
Publication Date: June 2011
pp. N/A
Although communication fabrics at the microarchitectural level are mainly composed of standard primitives such as queues and arbiters, to get an executable model one has to connect these primitives with glue logic to complete the description. In this paper...
 
System interconnect design exploration for embedded MPSoCs
Found in: System Level Interconnect Prediction, International Workshop on
By Chen-Ling Chou,Radu Marculescu,Umit Ogras,Satrajit Chatterjee,Michael Kishinevsky,Dmitrii Loukianov
Issue Date:June 2011
pp. 1-8
This paper presents a new approach for system interconnect design exploration of application-specific multi-processor systems-on-chip (MPSoCs). As a novel contribution, we develop an analytical model for network-based communication design space exploration...
 
Quick formal modeling of communication fabrics to enable verification
Found in: High-Level Design, Validation, and Test Workshop, IEEE International
By Satrajit Chatterjee, Michael Kishinevsky, Umit Y. Ogras
Issue Date:June 2010
pp. 42-49
Although communication fabrics at the microarchitectural level are mainly composed of standard primitives such as queues and arbiters, to get an executable model one has to connect these primitives with glue logic to complete the description. In this paper...
 
Physical-Aware Link Allocation and Route Assignment for Chip Multiprocessing
Found in: Networks-on-Chip, International Symposium on
By Nikita Nikitin, Satrajit Chatterjee, Jordi Cortadella, Mike Kishinevsky, Umit Ogras
Issue Date:May 2010
pp. 125-134
The architecture definition, design, and validation of the interconnect networks is a key step in the design of modern on-chip systems. This paper proposes a mathematical formulation of the problem of simultaneously defining the topology of the network and...
 
Boolean factoring and decomposition of logic networks
Found in: Computer-Aided Design, International Conference on
By Alan Mishchenko, Robert Brayton, Satrajit Chatterjee
Issue Date:November 2008
pp. 38-44
This paper presents new methods for restructuring logic networks based on fast Boolean techniques. The basis for these are 1) a cut-based view of a logic network, 2) exploiting the uniqueness and speed of disjoint-support decompositions, 3) a new heuristic...
 
On resolution proofs for combinational equivalence
Found in: Proceedings of the 44th annual conference on Design automation (DAC '07)
By Alan Mishchenko, Andreas Kuehlmann, Robert Brayton, Satrajit Chatterjee
Issue Date:June 2007
pp. 600-605
Modern combinational equivalence checking (CEC) engines are complicated programs which are difficult to verify. In this paper we show how a modern CEC engine can be modified to produce a proof of equivalence when it proves a miter unsatisfiable. If the CEC...
     
Improvements to combinational equivalence checking
Found in: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design (ICCAD '06)
By Alan Mishchenko, Niklas Een, Robert Brayton, Satrajit Chatterjee
Issue Date:November 2006
pp. 836-843
The paper explores several ways to improve the speed and capacity of combinational equivalence checking based on Boolean satisfiability (SAT). State-of-the-art methods use simulation and BDD/SAT sweeping on the input side (i.e. proving equivalence of some ...
     
Factor cuts
Found in: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design (ICCAD '06)
By Alan Mishchenko, Robert Brayton, Satrajit Chatterjee
Issue Date:November 2006
pp. 143-150
Enumeration of bounded size cuts is an important step in several logic synthesis algorithms such as technology mapping and re-writing. The standard algorithm does not scale beyond 6 or 7 inputs because it enumerates all cuts and there are too many of them....
     
DAG-aware AIG rewriting a fresh look at combinational logic synthesis
Found in: Proceedings of the 43rd annual conference on Design automation (DAC '06)
By Alan Mishchenko, Robert Brayton, Satrajit Chatterjee
Issue Date:July 2006
pp. 532-535
This paper presents a technique for preprocessing combinational logic before technology mapping. The technique is based on the representation of combinational logic using And-Inverter Graphs (AIGs), a networks of two-input ANDs and inverters. The optimizat...
     
Improvements to technology mapping for LUT-based FPGAs
Found in: Proceedings of the internation symposium on Field programmable gate arrays (FPGA'06)
By Alan Mishchenko, Robert Brayton, Satrajit Chatterjee
Issue Date:February 2006
pp. 41-49
The paper presents several improvements to state-of-the-art in FPGA technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD '04]. Improved cut enumeration computes all K-feasible cuts without pruning for up to 7 i...
     
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