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Displaying 1-48 out of 48 total
IntellBatt: Toward a Smarter Battery
Found in: Computer
By Suman K. Mandal, Rabi N. Mahapatra, Praveen S. Bhojwani, Saraju P. Mohanty
Issue Date:March 2010
pp. 67-71
IntellBatt, a novel multicell battery design, exploits cell characteristics to increase battery lifetime, ensure safe operation, and improve performance. Simulations using Li-ion cells in a portable DVD player show a 22 percent battery lifetime enhancement...
 
A PVT aware accurate statistical logic library for high-
Found in: Quality Electronic Design, International Symposium on
By Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos, Priyadarsan Patra
Issue Date:March 2009
pp. 47-54
The semiconductor industry is headed towards a new era of scaling and uncertainty with new key building blocks for the next-generation chips, the high-
 
Metrics to Quantify Steady and Transient Gate Leakage in Nanoscale Transistors: NMOS vs. PMOS Perspective
Found in: VLSI Design, International Conference on
By Elias Kougianos, Saraju P. Mohanty
Issue Date:January 2007
pp. 195-200
In this paper we explore the use of a set of novel design metrics for characterizing the impact of gate oxide tunneling current in nanometer CMOS devices and perform Monte Carlo simulations to analyze the effects of variations of Tox and VDD on the statist...
 
Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis
Found in: VLSI Design, International Conference on
By Saraju P. Mohanty, Elias Kougianos
Issue Date:January 2007
pp. 577-582
We present minimization methodologies and an algorithm for simultaneous scheduling, binding, and allocation for the reduction of total power and power fluctuation during behavioral synthesis. We consider resources of dual gate oxide thicknesses, dual thres...
 
Energy Efficient Scheduling for Datapath Synthesis
Found in: VLSI Design, International Conference on
By Saraju P. Mohanty, N. Ranganathan
Issue Date:January 2003
pp. 446
In this paper, we describe two new algorithms for data-path scheduling which aim at energy reduction while maintaining performance. The proposed algorithms, time constrained and resource constrained, utilize the concepts of multiple supply voltage and dyna...
 
A Framework for Energy and Transient Power Reduction during Behavioral Synthesis
Found in: VLSI Design, International Conference on
By Saraju P. Mohanty, N. Ranganathan
Issue Date:January 2003
pp. 539
In deep submicron and nanometer designs for battery driven portable applications, the minimization of total energy, average power, peak power, and peak power differential are equally important. In this paper, we propose a framework for simultaneous reducti...
 
iVAMS: Intelligent metamodel-integrated Verilog-AMS for circuit-accurate system-level mixed-signal design exploration
Found in: 2013 IEEE 24th International Conference on Application-specific Systems, Architectures and Processors (ASAP)
By Geng Zheng,Saraju P. Mohanty,Elias Kougianos,Oghenekarho Okobiah
Issue Date:June 2013
pp. 75-78
The gap between abstraction levels in analog design is a major obstacle for advancing analog and mixed-signal design automation. Intelligent surrogate models for low-level analog building blocks are needed to bridge behavioral and transistorlevel simulatio...
 
RAEF: A Power Normalized System-Level Reliability Analysis and Estimation Framework
Found in: 2012 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
By Rishad A. Shafik,Bashir M. Al-Hashimi,Jimson Mathew,Dhiraj Pradhan,Saraju P. Mohanty
Issue Date:August 2012
pp. 189-194
System-level reliability estimation is a crucial aspect in reliable design of embedded systems. Recently reported estimation techniques use separate measurements of power consumption and reliability to demonstrate the trade-offs between them. However, we w...
 
Metamodel-Assisted Fast and Accurate Optimization of an OP-AMP for Biomedical Applications
Found in: 2012 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
By Geng Zheng,Saraju P. Mohanty,Elias Kougianos
Issue Date:August 2012
pp. 273-278
The optimized OP-AMPs resulting out of a traditional flows, although may meet the given specifications after consuming significant design cycle time, do not guarantee an optimal system performance. In this paper, a three-step polynomial metamodel-assisted ...
 
Geostatistical-Inspired Metamodeling and Optimization of Nano-CMOS Circuits
Found in: 2012 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
By Oghenekarho Okobiah,Saraju P. Mohanty,Elias Kougianos
Issue Date:August 2012
pp. 326-331
With the continuous progression of semiconductor technology, nanoscale effects have become a persistent issue in the design of analog/mixed-signal (AMS) circuits. The cost of exploration and optimization of the design space increases to infeasible levels w...
 
Stochastic Gradient Descent Optimization for Low Power Nano-CMOS Thermal Sensor Design
Found in: 2012 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
By Oghenekarho Okobiah,Saraju P. Mohanty,Elias Kougianos,Oleg Garitselov,Geng Zheng
Issue Date:August 2012
pp. 285-290
The drive for ultra efficient and low-cost portable devices continues to push the need for low power circuit designs. The increasing transistor density and complexity of IC designs aggravates the task of producing efficient low power and low cost design. T...
 
Kriging-Assisted Ultra-Fast Simulated-Annealing Optimization of a Clamped Bitline Sense Amplifier
Found in: VLSI Design, International Conference on
By Oghenekarho Okobiah,Saraju P. Mohanty,Elias Kougianos,Oleg Garitselov
Issue Date:January 2012
pp. 310-315
Simulations using SPICE provide accurate design exploration but consume a considerable amount of time and can be infeasible for large circuits. The continued technology scaling requires that more circuit parameters are accounted for along with the process ...
 
Fast-Accurate Non-Polynomial Metamodeling for Nano-CMOS PLL Design Optimization
Found in: VLSI Design, International Conference on
By Oleg Garitselov,Saraju P. Mohanty,Elias Kougianos
Issue Date:January 2012
pp. 316-321
At the nanoscale domain, the simulation, design, and optimization time of the circuits have increased significantly due to high-integration density, increasing technology constraints, and complex device models. This necessitates fast design space explorati...
 
PVT-tolerant 7-Transistor SRAM Optimization via Polynomial Regression
Found in: Electronic System Design, International Symposium on
By Saraju P. Mohanty,Elias Kougianos
Issue Date:December 2011
pp. 39-44
Low power consumption, stability, and PVT-tolerance in Static Random Access Memories (SRAM) is essential for nanoscale System-on-Chip (SoC) designs. In this paper, a novel design flow is presented for optimizing a figure of merit called Power to Static-Noi...
 
Statistical Blockade Method for Fast Robustness Estimation and Compensation of Nano-CMOS Arithmetic Circuits
Found in: Electronic System Design, International Symposium on
By Luo Sun,Jimson Mathew,Dhiraj K. Pradhan,Saraju P. Mohanty
Issue Date:December 2011
pp. 194-199
The challenges for nano-CMOS based design engineers have been aggravated due to the introduction of variability into the design phase. One of the ways to understand the circuit behaviors under process variation is to analyze the rare events that may be ori...
 
Bee Colony Inspired Metamodeling Based Fast Optimization of a Nano-CMOS PLL
Found in: Electronic System Design, International Symposium on
By Oleg Garitselov,Saraju P. Mohanty,Elias Kougianos,Priyadarsan Patra
Issue Date:December 2011
pp. 6-11
The design and optimization complexity of analog/mixed-signal (AMS) components causes significant increase in the design cycle as the technology progresses towards deep nanoscale. This paper presents a two-tier approach to significantly reduce the design c...
 
Digital Nano-CMOS VLSI Design Courses in Electrical and Computer Engineering through Open-Source/Free Tools
Found in: Electronic System Design, International Symposium on
By Elias Kougianos, Saraju P. Mohanty, Priyadarsan Patra
Issue Date:December 2010
pp. 265-270
Digital VLSI design courses are a standard component in most electrical and computer engineering curricula. Electronic Design Automation (EDA) or Computer Aided Design (CAD) tools and frameworks are an integral and indispensable part of such courses. In th...
 
Nano-CMOS Mixed-Signal Circuit Metamodeling Techniques: A Comparative Study
Found in: Electronic System Design, International Symposium on
By Oleg Garitselov, Saraju P. Mohanty, Elias Kougianos, Priyadarsan Patra
Issue Date:December 2010
pp. 191-196
Fast design space exploration of complex nano-CMOS mixed-signal circuits is an important problem. In this paper, a design process flow that uses metamodels is introduced. In this flow the most important task is the sampling of the design space. In this pap...
 
Design of a Reconfigurable Embedded Data Cache
Found in: Electronic System Design, International Symposium on
By Ruchi Rastogi Bani, Saraju P. Mohanty, Elias Kougianos, Garima Thakral
Issue Date:December 2010
pp. 163-168
Performance and power consumption are very important aspects of embedded systems design. Several studies have shown that cache memory consumes as much as 50\% of the total power in such systems. Thus, the architecture of the cache governs both performance ...
 
A P4VT (Power Performance Process Parasitic Voltage Temperature) Aware Dual-VTh Nano-CMOS VCO
Found in: VLSI Design, International Conference on
By Saraju P. Mohanty, Dhruva Ghai, Elias Kougianos
Issue Date:January 2010
pp. 99-104
We present the design flow for a P4VT (Power-Performance-Process-Parasitic-Voltage-Temperature) aware voltage controlled oscillator (VCO). Through simulations, we have shown that parasitics, process, voltage and temperature have a drastic effect on the per...
 
A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM
Found in: VLSI Design, International Conference on
By Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan
Issue Date:January 2010
pp. 45-50
A novel design approach for simultaneous power and stability (static noise margin, SNM) optimization of nano-CMOS static random access memory (SRAM) is presented. A 45nm single-ended seven transistor SRAM is used as a case study. The SRAM is subjected to a...
 
Variability-aware optimization of nano-CMOS Active Pixel Sensors using design and analysis of Monte Carlo experiments
Found in: Quality Electronic Design, International Symposium on
By Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos
Issue Date:March 2009
pp. 172-178
We propose a novel design f ow for mismatch and processvariation aware optimization of nanoscale CMOS Active Pixel Sensor (APS) arrays. As a case study, an 8
 
VLSI architectures of perceptual based video watermarking for real-time copyright protection
Found in: Quality Electronic Design, International Symposium on
By Saraju P. Mohanty, Elias Kougianos, Wei Cai, Manish Ratnani
Issue Date:March 2009
pp. 527-534
For effective digital rights management (DRM) of multimedia in the framework of embedded systems, both watermarking and cryptography are necessary. In this paper, we present a watermarking algorithm and VLSI architecture that can insert a broadcaster's log...
 
A universal level converter towards the realization of energy efficient implantable drug delivery Nano-Electro-Mechanical-Systems
Found in: Quality Electronic Design, International Symposium on
By Saraju P. Mohanty, Dhruva Ghai, Elias Kougianos, Bharat Joshi
Issue Date:March 2009
pp. 673-679
Nano-Electro-Mechanical-Systems (NEMS) are a technological solution for building miniature systems which can be beneficial in terms of safety, efficacy, or convenience. Thus investigation is necessary for their usefulness in drug delivery. In order to be a...
 
Unified Challenges in Nano-CMOS High-Level Synthesis
Found in: VLSI Design, International Conference on
By Saraju P. Mohanty
Issue Date:January 2009
pp. 531
No summary available.
 
Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems
Found in: VLSI Design, International Conference on
By Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan
Issue Date:January 2009
pp. 307-312
Single-ended static random access memory (SESRAM) is well known for their tremendous potential of low active power and leakage dissipations. In this paper, we present a novel six-transistor (6T) SE-SRAM bitcell for low-Vdd and high speed embedded applicati...
 
A combined packet classifier and scheduler towards Net-Centric Multimedia Processor design
Found in: Computers in Education, International Conference on
By Saraju P. Mohanty, Dhruva Ghai, Elias Kougianos, Priyadarsan Patra
Issue Date:January 2009
pp. 1-2
We introduce a Net-centric Multimedia Processor (NMP) with built-in Digital Rights Management (DRM) facilities to facilitate internet protocol packet processing and video processing without use of the main CPU. Packet classification and scheduling are the ...
 
GPU-CPU multi-core for real-time signal processing
Found in: Computers in Education, International Conference on
By Saraju P. Mohanty
Issue Date:January 2009
pp. 1-2
Modern graphics cards are supported with powerful computational facilities for fast computation of vertex geometry and realistic rendering of 3D graphics. The introduction of programmable pipeline in the graphics processing units (GPU) has enabled configur...
 
Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) Design
Found in: Quality Electronic Design, International Symposium on
By Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos
Issue Date:March 2008
pp. 330-333
In this paper we present a parasitic aware, process variation tolerant optimization methodology that may be applied to nanoscale circuits to ensure better yield. A current-starved voltage controlled oscillator (VCO) is treated as a case study and to the be...
 
ILP Based Gate Leakage Optimization Using DKCMOS Library during RTL Synthesis
Found in: Quality Electronic Design, International Symposium on
By Saraju P. Mohanty
Issue Date:March 2008
pp. 174-177
In this paper dual-K (DKCMOS) technology is proposed as a method for gate leakage power reduction. An integer linear programming (ILP) based algorithm is proposed for its optimization during architectural synthesis. The algorithm uses device-level gate lea...
 
A Novel Invisible Color Image Watermarking Scheme Using Image Adaptive Watermark Creation and Robust Insertion-Extraction
Found in: Multimedia, International Symposium on
By Saraju P. Mohanty, Parthasarathy Guturu, Elias Kougianos, Nishikanta Pati
Issue Date:December 2006
pp. 153-160
In this paper we present a robust and novel strategic invisible approach for insertion-extraction of a digital watermark, a color image, into color images. The novelty of our scheme lies in determining a perceptually important sub-image in the host image s...
 
Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective
Found in: Quality Electronic Design, International Symposium on
By Saraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos
Issue Date:March 2006
pp. 564-569
As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has become a major component of total power dissipation. Use of dielectrics of higher permittivity (Dual-K) or use of silicon dioxide of higher thicknesses (Dual-T ) a...
 
Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits
Found in: VLSI Design, International Conference on
By Saraju P. Mohanty, Elias Kougianos
Issue Date:January 2006
pp. 83-88
For a nanoCMOS of sub-65nm technology, where the gate oxide (SiO2) thickness is very low, the gate leakage is one of the major components of power dissipation. In this paper, we provide analytical models to describe the tunneling current and propagation de...
 
A High-Performance VLSI Architecture for Advanced Encryption Standard (AES) Algorithm
Found in: VLSI Design, International Conference on
By Naga M. Kosaraju, Murali Varanasi, Saraju P. Mohanty
Issue Date:January 2006
pp. 481-484
In this paper we present a high-performance, high throughput, and area efficient architecture for the VLSI implementation of the AES algorithm. The subkeys, required for each round of the Rijndael algorithm, are generated in real-time by the key-scheduler ...
 
Design of a Low Power Image Watermarking Encoder Using Dual Voltage and Frequency
Found in: VLSI Design, International Conference on
By Saraju P. Mohanty, N. Ranganathan, K. Balakrishnan
Issue Date:January 2005
pp. 153-158
In this paper, we propose a VLSI architecture and provide prototype implementation of a chip that can insert both invisible and visible watermarks in DCT domain. To our knowledge, this is the firstever low power watermarking chip having such watermarking f...
 
ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis
Found in: VLSI Design, International Conference on
By Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi
Issue Date:January 2004
pp. 745
The reduction of peak power, peak power differential, average power and energy are equally important in the design of low-power battery driven portable applications. In this paper, we introduce a parameter called
 
VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design
Found in: VLSI Design, International Conference on
By Saraju P. Mohanty, N. Ranganathan, Ravi K. Namballa
Issue Date:January 2004
pp. 1063
Watermarking is the process that embeds data called a watermark into a multimedia object for its copyright protection. The digital watermarks can be visible to a viewer on careful inspection or completely invisible and cannot be easily recovered without an...
 
Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling
Found in: Computer Design, International Conference on
By Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi
Issue Date:October 2003
pp. 441
We model the power fluctuation as cycle-to-cycle power gradient and minimize the mean of the power gradients using ILP. We propose scheduling schemes for three modes of datapath design : single supply voltage and single frequency (SVSF), multiple supply vo...
 
Peak Power Minimization Through Datapath Scheduling
Found in: VLSI, IEEE Computer Society Annual Symposium on
By Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi
Issue Date:February 2003
pp. 121
In this paper, we describe new integer linear programming models and algorithms for datapath scheduling that aim at minimizing peak power while maintaining performance. The first algorithm, MVDFC combines both multiple supply voltages and dynamic frequency...
 
Datapath Scheduling using Dynamic Frequency Clocking
Found in: VLSI, IEEE Computer Society Annual Symposium on
By Saraju P. Mohanty, N. Ranganathan, V. Krishna
Issue Date:April 2002
pp. 0065
In this paper, we describe a new datapath scheduling algorithm called DFCS based on the concept of dynamic frequency clocking. In dynamic frequency clocking scheme, all functional units in the datapath are driven by a single clock line that switches freque...
 
Special section on new circuit and architecture-level solutions for multidiscipline systems
Found in: ACM Journal on Emerging Technologies in Computing Systems (JETC)
By Saraju P. Mohanty
Issue Date:August 2012
pp. 1-2
Companies acquire personal information from phone, World Wide Web, or email in order to sell or send an advertisement about their product. However, when this information is acquired, moved, copied, or edited, the data may lose its quality. Often, the use o...
     
Towards robust nano-CMOS sense amplifier design: a dual-threshold versus dual-oxide perspective
Found in: Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI (GLSVLSI '11)
By Elias Kougianos, Mahesh Poolakkaparambil, Oghenekarho Okobiah, Saraju P. Mohanty
Issue Date:May 2011
pp. 145-150
This paper presents research leading to robust nano-CMOS sense amplifier design by incorporating process variation early in the design process. The effects of process variation are analyzed on the performance of a conventional voltage sense amplifier which...
     
Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO
Found in: Proceedings of the 19th ACM Great Lakes symposium on VLSI (GLSVLSI '09)
By Dhruva Ghai, Elias Kougianos, Saraju P. Mohanty
Issue Date:May 2009
pp. 375-376
In this paper, we present the design of a P4 (Power-Performance-Process-Parasitic) aware voltage controlled oscillator (VCO) at nano-CMOS technologies. Through simulations, we have shown that parasitics and process have a drastic effect on the performance ...
     
Invisible watermarking based on creation and robust insertion-extraction of image adaptive watermarks
Found in: ACM Transactions on Multimedia Computing, Communications, and Applications (TOMCCAP)
By Bharat K. Bhargava, Saraju P. Mohanty
Issue Date:November 2008
pp. 1-22
This article presents a novel invisible robust watermarking scheme for embedding and extracting a digital watermark in an image. The novelty lies in determining a perceptually important subimage in the host image. Invisible insertion of the watermark is pe...
     
IntellBatt: towards smarter battery design
Found in: Proceedings of the 45th annual conference on Design automation (DAC '08)
By Praveen S. Bhojwani, Rabi N. Mahapatra, Saraju P. Mohanty, Suman K. Mandal
Issue Date:June 2008
pp. 1-30
Battery lifetime and safety are primary concerns in the design of battery operated systems. Lifetime management is typically supervised by the system via battery-aware task scheduling, while safety is managed on the battery side via features deployed into ...
     
Energy-efficient datapath scheduling using multiple voltages and dynamic clocking
Found in: ACM Transactions on Design Automation of Electronic Systems (TODAES)
By N. Ranganathan, Saraju P. Mohanty
Issue Date:April 2005
pp. 330-353
Recently, dynamic frequency scaling has been explored at the CPU and system levels for power optimization. Low-power datapath scheduling using multiple supply voltages has been well researched. In this work, we develop new datapath scheduling algorithms th...
     
Simultaneous peak and average power minimization during datapath scheduling for DSP processors
Found in: Proceedings of the 13th ACM Great Lakes Symposium on VLSI (GLSVLSI '03)
By N. Ranganathan, Saraju P. Mohanty, Sunil K. Chappidi
Issue Date:April 2003
pp. 215-220
The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using deep submicron and nanometer technology, the peak power, peak power differen...
     
A dual watermarking technique for images
Found in: Proceedings of the seventh ACM international conference on Multimedia (Part 2) (MULTIMEDIA '99)
By K. R. Ramakrishnan, Mohan Kankanhalli, Saraju P. Mohanty
Issue Date:October 1999
pp. 49-51
In this paper we propose and implement an efficient scheme for automatically detecting the abrupt shot changes in a video stream compressed in MPEG video format. In the proposed scheme, the type of each macroblock in a B-frame is compared with the type of ...
     
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