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Displaying 1-50 out of 54 total
User-Constrained Test Architecture Design for Modular SOC Testing
Found in: European Test Symposium, IEEE
By Ludovic Krundel, Sandeep Kumar Goel, Erik Jan Marinissen, Marie-Lise Flottes, Bruno Rouzeyre
Issue Date:May 2004
pp. 80-85
This paper discusses the extensions to the automatic SOC test architecture optimization tool TR-ARCHITECT that allow the user to partially specify the resulting test architecture. We describe a novel Test Architecture Specification (TAS) language, in which...
 
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Sandeep Kumar Goel, Erik Jan Marinissen
Issue Date:March 2005
pp. 44-49
Multi-site testing is a popular and effective way to increase test throughput and reduce test costs. We present a test throughput model, in which we focus on wafer testing, and consider parameters like test time, index time, abort-on-fail, and contact yiel...
 
IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores
Found in: Test Conference, International
By Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty
Issue Date:October 2004
pp. 1203-1212
Most system-on-chips (SOCs) today contain hierarchical cores that have multiple levels of design hierarchy. An efficient wrapper design for hierarchical cores is necessary to facilitate modular testing of SOCs. In most of the prior work on wrapper design f...
 
Test Scheduling for Modular SOCs in an Abort-on-Fail Environment
Found in: European Test Symposium, IEEE
By Urban Ingelsson, Sandeep Kumar Goel, Erik Larsson, Erik Jan Marinissen
Issue Date:May 2005
pp. 8-13
Complex SOCs are increasingly tested in a modular fashion, which enables us to record the yield-per-module. In this paper, we consider the yield-per-module as the pass probability of the module?s manufacturing test. We use it to exploit the abort-on-fail f...
 
Test Infrastructure Design for the Nexperia™ Home Platform PNX8550 System Chip
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Sandeep Kumar Goel, Kuoshu Chiu, Erik Jan Marinissen, Toan Nguyen, Steven Oostdijk
Issue Date:February 2004
pp. 30108
Philips has adopted a modular manufacturing test strategy for its SOCs that are part of the Nexperia™ Home Platform. The on-chip infrastructure that enables modular testing consists of wrappers and Test Access Mechanisms (TAMs). Optimizing that infrastruct...
 
Control-Aware Test Architecture Design for Modular SOC Testing
Found in: European Test Workshop, IEEE
By Sandeep Kumar Goel, Erik Jan Marinissen
Issue Date:May 2003
pp. 57
This paper deals with control-aware test architecture design for SOCs. The term test control refers to the control of mode of operation of all modules connected in different TAMs and the execution of the modules tests. We classify test control into two cat...
 
Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Sandeep Kumar Goel, Erik Jan Marinissen
Issue Date:March 2003
pp. 10738
This paper extends existing SOC test architecture design approaches that minimize required tester vector memory depth and test application time, with the capability to minimize the wire length required by the test architecture. We present a simple, yet eff...
 
Effective and Efficient Test Architecture Design for SOCs
Found in: Test Conference, International
By Sandeep Kumar Goel, Erik Jan Marinissen
Issue Date:October 2002
pp. 529
This paper deals with the design of test architectures for modular SOC testing. These architectures consist of wrappers and TAMs. For a given SOC, with specified parameters of modules and their tests, we design architectures which minimize the required ATE...
 
A Novel Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips
Found in: European Test Workshop, IEEE
By Sandeep Kumar Goel, Erik Jan Marinissen
Issue Date:May 2002
pp. 7
This paper deals with the design of SOC test architectures which are efficient with respect to required ATE vector memory depth and test application time. We advocate the usage of a TestRail Architecture, as this architecture, unlike others, allows not onl...
 
Cluster-Based Test Architecture Design for System-on-Chip
Found in: VLSI Test Symposium, IEEE
By Sandeep Kumar Goel, Erik Jan Marinissen
Issue Date:May 2002
pp. 0259
A test architecture for an SOC consists of a number of Test Access Mechanisms that connect to wrapped cores. This paper presents a new test architecture, named the TestRail Architecture, that is a hybrid form of the known Daisychain and Distribution Archit...
 
Wrapper Design for Embedded Core Test
Found in: Test Conference, International
By Erik Jan Marinissen, Sandeep Kumar Goel, Maurice Lousberg
Issue Date:October 2000
pp. 911
A wrapper is a thin shell around the core, that provides the switching between functional, and core-internal and core-external test modes. Together with a test access mechanism (TAM), the core test wrapper forms the test access infrastructure to embedded r...
 
Hybrid Satisfiability Techniques
Found in: Information Technology: New Generations, Third International Conference on
By Sandeep Kumar Singla, Pradeep Kumar Jaswal
Issue Date:April 2010
pp. 281-284
Satisfiability Techniques helps in deciding if there is a truth assignment for the symbols that appear in a Boolean function such that it assigns the value true to the Boolean Function. However satisfiability can be proved using Truth Tables, but design of...
 
Fuzzy mathematical solution's of Customer Relationship Management financial sector for current economic era
Found in: Computer Science and Information Technology, International Conference on
By Manoj Kumar Jain,A. K. Dalela,Sandeep Kumar Tiwari
Issue Date:August 2009
pp. 344-348
Today, many businesses such as banks, insurance companies, and other service providers realize the importance of Customer Relationship Management (CRM) and its potential to help them acquire new customers retain existing ones and maximize their lifetime va...
 
DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks
Found in: 2012 IEEE International Test Conference (ITC)
By Sergej Deutsch,Brion Keller,Vivek Chickermane,Subhasish Mukherjee,Navdeep Sood,Sandeep Kumar Goel,Ji-Jan Chen,Ashok Mehta,Frank Lee,Erik Jan Marinissen
Issue Date:November 2012
pp. 1-10
Three-dimensional (3D) die stacking is an emerging integration technology which brings benefits with respect to heterogeneous integration, inter-die interconnect density, performance, and energy efficiency, and component size and yield. In the past, we hav...
 
An Approach to Effectively Transfer Knowledge and Accelerate the Movement of Software Services Offshore
Found in: 2012 7th IEEE International Conference on Global Software Engineering (ICGSE)
By Sandeep Kumar,Ajit Krishna,V.S. Mani,B.K. Kulkarni,Carlos Arglebe
Issue Date:August 2012
pp. 212-216
Offshore team spend considerable amount of time to acquire the skill to become fully productive in providing software services. We describe a knowledge transfer approach to effectively accelerate offshoring software services by shortening the knowledge tra...
 
Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base
Found in: Asian Test Symposium
By Chun-Chuan Chi,Erik Jan Marinissen,Sandeep Kumar Goel,Cheng-Wen Wu
Issue Date:November 2011
pp. 451-456
2.5D Stacked ICs (2.5D-SICs) consist of multiple active dies (or 3D towers of active dies), which are placed side-by-side on top of and interconnected through a passive silicon interposer base which contains Through-Silicon Vias (TSVs). A previously presen...
 
Efficient VLSI Architectures for the Hadamard Transform Based on Offset-Binary Coding and ROM Decomposition
Found in: VLSI, IEEE Computer Society Annual Symposium on
By B. Sandeep Kumar, Vikramkumar Pudi, K. Sridharan
Issue Date:July 2011
pp. 347-348
We present efficient architectures for the discrete Hadamard transform based on two techniques, namely offset binary coding and ROM decomposition. The proposed architectures do not require large size ROMs in comparison to a recently proposed solution. Resu...
 
Circuit Topology-Based Test Pattern Generation for Small-Delay Defects
Found in: Asian Test Symposium
By Sandeep Kumar Goel, Krishnendu Chakrabarty, Mahmut Yilmaz, Ke Peng, Mohammad Tehranipoor
Issue Date:December 2010
pp. 307-312
For sub-nanometer designs, testing for small-delay defects (SDDs) is essential to achieve low defect escapes for the manufactured silicon. Existing solutions for testing SDDs are not practical for high-volume production environments due to large pattern co...
 
Neural Network: A Machine Learning Technique for Tertiary Structure Prediction of Proteins from Peptide Sequences
Found in: Advances in Computing, Control, and Telecommunication Technologies, International Conference on
By Sandeep Kumar Kushwaha, Madhvi Shakya
Issue Date:December 2009
pp. 98-101
The current work has deduced the novel method for tertiary structure prediction of various important unpredicted proteins through machine learning technique neural network. Multi-layer perceptron architecture has been developed to predict the tertiary stru...
 
Dynamic Partial Reconfigurable Embedded System to Achieve Hardware Flexibility Using 8051 Based RTOS on Xilinx FPGA
Found in: Advances in Computing, Control, and Telecommunication Technologies, International Conference on
By Jitendra B. Zalke, Sandeep Kumar Pandey
Issue Date:December 2009
pp. 684-686
Field Programmable Gate Arrays (FPGAs) are increasingly being used for many systems and efficient System-on-a-Chip (SOC) designs. Hence, dynamic partial self reconfiguration (DPSR) of the FPGA can be regarded as one of essentials of making hardware flexibl...
 
Multi-layer Perceptron Architecture for Tertiary Structure Prediction of Helical Content of Proteins from Peptide Sequences
Found in: Advances in Recent Technologies in Communication and Computing, International Conference on
By Sandeep Kumar Kushwaha, Madhvi Shakya
Issue Date:October 2009
pp. 465-467
The purpose of the present study is to deduce the novel method for tertiary structure prediction of various important unpredicted proteins i.e. metabolic, regulatory, signalling etc. due unavailability of template structure. Multi-layer perception architec...
 
Universal digital device automation and control
Found in: Computer Science and Information Technology, International Conference on
By Sandeep Kumar,Mohammed A. Qadeer
Issue Date:August 2009
pp. 490-494
The Bluetooth-Kit (BT-Kit) and Microprocessor controlled device/appliance based automation are restricted to less flexible and dedicated control. This paper presents a digital method for controlling these devices in a form that is very flexible and can be ...
 
Metamodeling: An Emerging Representation Paradigm for System-Level Design
Found in: IEEE Design and Test of Computers
By Alberto Sangiovanni-Vincentelli, Sandeep Kumar Shukla, Janos Sztipanovits, Guang Yang, Deepak A. Mathaikutty
Issue Date:May 2009
pp. 54-69
<p>Editor's note:</p><p>The use of metamodeling in system design allows abstraction of concepts germane to a number of varying modeling domains, and provides the ability of exploiting meta-information for a variety of system design tasks ...
 
Effective and Efficient Test Pattern Generation for Small Delay Defect
Found in: VLSI Test Symposium, IEEE
By Sandeep Kumar Goel, Narendra Devta-Prasanna, Ritesh P. Turakhia
Issue Date:May 2009
pp. 111-116
Testing for small delay defects is critical to guarantee that the manufactured silicon is timing-related defect free and to reduce quality loss associated with delay defects. Commercial solutions available for testing of small delay defects result in very ...
 
Energy-Efficient Thermal-Aware Task Scheduling for Homogeneous High-Performance Computing Data Centers: A Cyber-Physical Approach
Found in: IEEE Transactions on Parallel and Distributed Systems
By Qinghui Tang, Sandeep Kumar S. Gupta, Georgios Varsamopoulos
Issue Date:November 2008
pp. 1458-1472
High Performance Computing data centers have been rapidly growing, both in number and in size. Thermal management of data centers can address dominant problems associated with cooling such as the recirculation of hot air from the equipment outlets to their...
 
A Survey of Lightweight-Cryptography Implementations
Found in: IEEE Design and Test of Computers
By Thomas Eisenbarth, Sandeep Kumar, Christof Paar, Axel Poschmann, Leif Uhsadel
Issue Date:November 2007
pp. 522-533
The upcoming pervasive computing age will lead to an increased demand for security for applications ranging from RFIDs and smart cards to mobile devices. Lightweight cryptography is a key tool for building strong security solutions for pervasive devices. D...
 
Continuous Verification Using Multimodal Biometrics
Found in: IEEE Transactions on Pattern Analysis and Machine Intelligence
By Terence Sim, Sheng Zhang, Rajkumar Janakiraman, Sandeep Kumar
Issue Date:April 2007
pp. 687-700
Conventional verification systems, such as those controlling access to a secure room, do not usually require the user to reauthenticate himself for continued access to the protected resource. This may not be sufficient for high-security environments in whi...
 
Optimum Digit Serial GF(2^m) Multipliers for Curve-Based Cryptography
Found in: IEEE Transactions on Computers
By Sandeep Kumar, Thomas Wollinger, Christof Paar
Issue Date:October 2006
pp. 1306-1311
Digit Serial Multipliers are used extensively in hardware implementations of elliptic and hyperelliptic curve cryptography. This contribution shows different architectural enhancements in Least Significant Digit (LSD) multiplier for binary fields GF(2^m). ...
 
Testing and Diagnosis of Power Switches in SOCs
Found in: European Test Symposium, IEEE
By Sandeep Kumar Goel, Maurice Meijer, Jose Pineda de Gyvez
Issue Date:May 2006
pp. 145-150
The use of power switches in modern system chips (SOCs) is inevitable as they allow for efficient on-chip static power management. Leakage is today one of the main hurdles in low-power applications. Power switches enable power gating functionality, i.e., o...
 
COPACOBANA A Cost-Optimized Special-Purpose Hardware for Code-Breaking
Found in: Field-Programmable Custom Computing Machines, Annual IEEE Symposium on
By Sandeep Kumar, Christof Paar, Jan Pelzl, Gerd Pfeiffer, Manfred Schimmler
Issue Date:April 2006
pp. 311-312
Cryptanalysis of symmetric and asymmetric ciphers is computationally extremely demanding. Since the security parameters of almost all practical crypto algorithms are chosen such that attacks with conventional computers are computationally infeasible, the o...
 
Using Continuous Biometric Verification to Protect Interactive Login Sessions
Found in: Computer Security Applications Conference, Annual
By Sandeep Kumar, Terence Sim, Rajkumar Janakiraman, Sheng Zhang
Issue Date:December 2005
pp. 441-450
In this paper we describe the theory, architecture, implementation, and performance of a multi-modal passive biometric verification system that continually verifies the presence/ participation of a logged-in user. We assume that the user logged in using st...
 
Optimal Offline and Online Registration Techniques for Location Management with Overlapping Registration Areas
Found in: IEEE Transactions on Mobile Computing
By Georgios Varsamopoulos, Sandeep Kumar S. Gupta
Issue Date:September 2005
pp. 474-488
Personal Communication Services (PCS) standards such as the IS-41 and the GSM use a location management scheme which is based on registration areas (RA). Overlapping of registration areas has been proposed to reduce the overhead of location updates in such...
 
Using Continuous Face Verification to Improve Desktop Security
Found in: Applications of Computer Vision and the IEEE Workshop on Motion and Video Computing, IEEE Workshop on
By Rajkumar Janakiraman, Sandeep Kumar, Sheng Zhang, Terence Sim
Issue Date:January 2005
pp. 501-507
In this paper we describe the architecture, implementation, and performance of a face verification system that continually verifies the presence of a logged-in user at a computer console. It maintains a sliding window of about ten seconds of verification d...
 
A Behavioral Type Inference System for Compositional System-on-Chip Design
Found in: Application of Concurrency to System Design, International Conference on
By Jean-Pierre Talpin, David Berner, Sandeep Kumar Shukla, Paul Le Guernic, Abdoulaye Gamatié, Rajesh Gupta
Issue Date:June 2004
pp. 47
The design productivity gap has been recognized by the semiconductor industry as one of the major threats to the continued growth of system-on-chips and embedded systems. Ad-hoc system-level design methodologies, that lifts modeling to higher levels of abs...
   
Modeling and Validating Globally Asynchronous Design in Synchronous Frameworks
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Mohammad Reza Mousavi, Paul Le Guernic, Jean-Pierre Talpin, Sandeep Kumar Shukla, Twan Basten
Issue Date:February 2004
pp. 10384
We lay a foundation for modeling and validation of asynchronous designs in a multi-clock synchronous programming model. This allows us to study properties of globally asynchronous systems using synchronous simulation and model-checking toolkits. Our approa...
   
Guest Editorial: Special Section on Data Management Systems and Mobile Computing
Found in: IEEE Transactions on Computers
By Pradip K. Srimani, Wang-Chien Lee, Sandeep Kumar S. Gupta
Issue Date:October 2002
pp. 1121-1123
No summary available.
 
Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints
Found in: Test Conference, International
By Vikram Iyengar, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty
Issue Date:October 2002
pp. 1159
We present a two-step solution to the problem of test resource optimization for multi-site testing of embedded-core-based SOCs. In Step 1, an efficient technique based on enhanced rectangle packing is used to design the wrapper/TAM architecture such that t...
 
Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips
Found in: Test Conference, International
By Sandeep Kumar Goel, Bart Vermeulen
Issue Date:October 2002
pp. 1103
To debug a digital chip with a scan-based debug methodology, the chip is stopped at a certain point in time in the application. The state of the flip-flops and the memory elements is observed and compared with the simulation results. If the chip contains m...
 
Design for Debug: Catching Design Errors in Digital Chips
Found in: IEEE Design and Test of Computers
By Bart Vermeulen, Sandeep Kumar Goel
Issue Date:May 2002
pp. 37-45
<p>For large, complex ICs, engineers need efficient techniques for debugging first silicon. The system presented here consists of an on-chip debug infrastructure and supporting debugger software,which interacts with the infrastructure to make the chi...
 
Precise Call Graph Construction for OO Programs in the Presence of Virtual Functions
Found in: Parallel Processing, International Conference on
By Deepankar Bairagi, Dharma P. Agrawal, Sandeep Kumar
Issue Date:August 1997
pp. 412
Several intra- and inter-procedural program analysis techniques form the backbone of an optimizing and parallelizing compiler. The efficacy of these analyses depends upon how precise the call graph is. However, due to lack of exact type information for obj...
 
Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study
Found in: 2013 IEEE International Test Conference (ITC)
By Sandeep Kumar Goel,Saman Adham,Min-Jer Wang,Ji-Jan Chen,Tze-Chiang Huang,Ashok Mehta,Frank Lee,Vivek Chickermane,Brion Keller,Thomas Valind,Subhasish Mukherjee,Navdeep Sood,Jeongho Cho,Hayden Hyungdong Lee,Jungi Choi,Sangdoo Kim
Issue Date:September 2013
pp. 1-10
Recent advances in semiconductor process technology especially interconnects using Through Silicon Vias (TSVs) enable the heterogeneous system integration where dies are implemented in dedicated, optimized process technologies and stacked in a 3D form. TSM...
   
DfT Architecture for 3D-SICs with Multiple Towers
Found in: European Test Symposium, IEEE
By Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu
Issue Date:May 2011
pp. 51-56
Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs) provide attractive benefits such as smaller form factor, higher performance, and lower power. So far, prior work on Design-for-Testability (DfT) only focused on 3D-SICs consisting...
 
Fast and Efficient On-Chip Interconnection Delay Modeling for High Speed VLSI Systems
Found in: Emerging Trends in Engineering & Technology, International Conference on
By A.R. Aswatha, T. Basavaraju, Sandeep Kumar. S
Issue Date:July 2008
pp. 414-417
Timing driven physical design, synthesis, and optimization tools need efficient closed-form delay models for estimating the delay associated with each net in an integrated circuit (IC) design. The total number of nets in a modern IC design has increased dr...
 
Polychrony for Formal Refinement-Checking in a System-Level Design Methodology
Found in: Application of Concurrency to System Design, International Conference on
By Jean-Pierre Talpin, Paul Le Guernic, Sandeep Kumar Shukla, Rajesh Gupta, Frédéric Doucet
Issue Date:June 2003
pp. 9
The productivity gap incurred by the rising complexity of the system-on-chip design have necessitated newer design paradigms to be introduced based on system-level design languages. A gating factors for widespread adoption of these new paradigms is a lack ...
   
Polychrony for Refinement-Based Design
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Jean-Pierre Talpin, Paul Guernic, Sandeep Kumar Shukla, Rajesh Gupta, Frédéric Doucet
Issue Date:March 2003
pp. 11172
Rising complexities and performances of integrated circuits and systems, shortening time-to-market demands for electronic equipments, growing installed bases of intellectual property, requirements for adapting existing Ips with new services, all stress hig...
   
Core-Based Scan Architecture for Silicon Debug
Found in: Test Conference, International
By Bart Vermeulen, Tom Waayers, Sandeep Kumar Goel
Issue Date:October 2002
pp. 638
In this paper, we present a core-based scan architecture for silicon debug, which is currently being standardized within Philips. The reasons behind the core-based debug architecture, together with implementation details, are described. The choices that we...
 
Securing the IP-based internet of things with HIP and DTLS
Found in: Proceedings of the sixth ACM conference on Security and privacy in wireless and mobile networks (WiSec '13)
By Jan Henrik Ziegeldorf, Sandeep Kumar
Issue Date:April 2013
pp. 119-124
The IP-based Internet of Things (IoT) refers to the pervasive interaction of smart devices and people enabling new applications by means of new IP protocols such as 6LoWPAN and CoAP. Security is a must, and for that we need a secure architecture in which a...
     
Test challenges in designing complex 3D chips: what is on the horizon for EDA industry?
Found in: Proceedings of the International Conference on Computer-Aided Design (ICCAD '12)
By Sandeep Kumar Goel
Issue Date:November 2012
pp. 273-273
Recent advances in semiconductor process technology especially interconnects using Through-Silicon Vias (TSVs) enable heterogeneous system integration where dies are implemented in dedicated, optimized process technologies and then stacked together to form...
     
A comparative study on homology modeling of P-glycoprotein (P-gp) structure using computational approach
Found in: Proceedings of the CUBE International Information Technology Conference (CUBE '12)
By Anurag Pal, Debahuti Mishra, Sandeep Kumar Satapathy, Shruti Mishra
Issue Date:September 2012
pp. 424-428
Proteins are composition of amino acid. These amino acids mainly form thousands of different proteins. P-glycoprotein (P-gp), one of the protein which is one of the plasma membrane and xenobiotic transport protein. It transports a variety of drug substrate...
     
Specification mining in concurrent and distributed systems
Found in: Proceeding of the 33rd international conference on Software engineering (ICSE '11)
By Sandeep Kumar
Issue Date:May 2011
pp. 1161-1163
Dynamic specification mining involves discovering software behavior from traces for the purpose of program comprehension and bug detection. However, in concurrent/distributed programs, the inherent partial order relationships among events occurring across ...
     
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