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Displaying 1-39 out of 39 total
Architectural, System Level and Protocol Level Techniques for Power Optimization for Networked Embedded Systems
Found in: VLSI Design, International Conference on
By Luca Benini, Sandeep K. Shukla, Rajesh K. Gupta
Issue Date:January 2005
pp. 18
No summary available.
   
Guest Editors' Introduction: Special Section on System-Level Design and Validation of Heterogeneous Chip Multiprocessors
Found in: IEEE Transactions on Computers
By Zeljko Zilic,Prabhat Mishra,Sandeep K. Shukla
Issue Date:February 2013
pp. 209-210
The three papers in this special section focus on system-level design and validation of heterogeneous chip multiprocessors.
 
Guest Editors' Introduction: Special Section on Science of Design for Safety Critical Systems
Found in: IEEE Transactions on Computers
By Sandeep K. Shukla, Jean-Pierre Talpin
Issue Date:August 2011
pp. 1057-1058
No summary available.
 
Guest Editors' Introduction to the Special Section on Programming Architectures for Embedded Systems
Found in: IEEE Transactions on Computers
By Sandeep K. Shukla, Jean-Pierre Talpin
Issue Date:October 2008
pp. 1297-1299
No summary available.
 
Guest Editors' Introduction: GALS Design and Validation
Found in: IEEE Design and Test of Computers
By Mike Kishinevsky, Sandeep K. Shukla, Kenneth S. Stevens
Issue Date:September 2007
pp. 414-416
Globally asynchronous, locally synchronous (GALS) design has grown in popularity in both academia and industry. Breaking the synchrony assumption in digital design is often unsettling for designers, and to alleviate the difficulty, researchers in EDA have ...
 
Guest Editors' Introduction: Challenges for Reliable Design at the Nanoscale
Found in: IEEE Design and Test of Computers
By R. Iris Bahar, Mehdi B. Tahoori, Sandeep K. Shukla, Fabrizio Lombardi
Issue Date:July 2005
pp. 295-297
This special issue contains four articles to covering techniques and applications for the reliable design of nanoscale systems; the techniques aim to circumvent the high defect rates and transient errors expected in advanced nanoscale technologies. As nano...
 
Teaching Game Theory for Computer Engineering
Found in: Microelectronics Systems Education, IEEE International Conference on/Multimedia Software Engineering, International Symposium on
By Sandeep K. Shukla
Issue Date:June 2005
pp. 41-42
Micro-economic game theory has been used for analysis of economic, political, and social conflict and cooperation scenarios since the seminal work of Cournot and Stackelberg in the nineteenth century, and the works of von Neumann and his colleagues in the ...
   
A Model Checking Approach to Evaluating System Level Dynamic Power Management Policies for Embedded Systems
Found in: High-Level Design, Validation, and Test Workshop, IEEE International
By Sandeep K. Shukla, Rajesh K. Gupta
Issue Date:December 2001
pp. 53
System Level Power Management policies are typically based on moving the system to various power management states, in order to achieve minimum wastage of power. The major challenge in devising such strategies is that the input task arrival rates to a syst...
 
High Level Modeling and Validation Methodologies for Embedded Systems: Bridging the Productivity Gap
Found in: VLSI Design, International Conference on
By Sandeep K. Shukla, Jean Pierre Talpin, Stephen A. Edwards, Rajesh K. Gupta
Issue Date:January 2003
pp. 9
No summary available.
   
Efficient Simulation of Synthesis-Oriented System Level Designs
Found in: System Synthesis, International Symposium on
By Rajesh K. Gupta, Sandeep K. Shukla, Nick Savoiu
Issue Date:October 2002
pp. 168-173
Modeling for synthesis and modeling for simulation seem to be two competing goals in the context of C++-based modeling frameworks. One of the reasons is while most hardware systems have some inherent parallelism efficiently expressing it depends on whether...
 
Embedding Polychrony into Synchrony
Found in: IEEE Transactions on Software Engineering
By Jens Brandt,Mike Gemunde,Klaus Schneider,Sandeep K. Shukla,Jean-Pierre Talpin
Issue Date:July 2013
pp. 917-929
This paper presents an embedding of polychronous programs into synchronous ones. Due to this embedding, it is not only possible to deepen the understanding of these different models of computation, but, more importantly, it is possible to transfer compilat...
 
A detailed analysis of the effective-load-carrying-capacity behavior of plug-in electric vehicles in the power grid
Found in: Innovative Smart Grid Technologies, IEEE PES
By Soumyo V. Chakraborty,Sandeep K. Shukla,James Thorp
Issue Date:January 2012
pp. 1-8
We performed a study of plug-in electric vehicle (PEV) vehicle-to-grid (V2G) operations to characterize the behavior of effective load carrying capacity (ELCC) contributed by the PEVs. We leveraged the V2G simulation framework developed in [1] and used wid...
 
System level simulation guided approach to improve the efficacy of clock-gating
Found in: High-Level Design, Validation, and Test Workshop, IEEE International
By Sumit Ahuja, Wei Zhang, Sandeep K. Shukla
Issue Date:June 2010
pp. 9-16
Clock-gating is a well known technique to reduce dynamic power consumption of a hardware design. In any clock-gating based power reduction flow, automatic selection of appropriate registers and/or register banks is extremely time-consuming because power an...
 
A Methodology for Power Aware High-Level Synthesis of Co-processors from Software Algorithms
Found in: VLSI Design, International Conference on
By Sumit Ahuja, Wei Zhang, Avinash Lakshminarayana, Sandeep K. Shukla
Issue Date:January 2010
pp. 282-287
Hardware co-processors are used for accelerating specific compute-intensive tasks dedicated to video/audio codec, encryption/decryption, etc. Since many of these data-processing tasks already have efficient software algorithms, one could reuse those to syn...
 
Model-Driven Engineering and Safety-Critical Embedded Software
Found in: Computer
By Sandeep K. Shukla
Issue Date:September 2009
pp. 93-95
Implementations embodied in a formally defined language with unambiguous semantics and a sound surrounding correctness for preserving refinement methodology make safety-critical software even safer.
 
Hardware Coprocessor Synthesis from an ANSI C Specification
Found in: IEEE Design and Test of Computers
By Sumit Ahuja, Swathi T. Gurumani, Chad Spackman, Sandeep K. Shukla
Issue Date:July 2009
pp. 58-67
<p>Editor's note:</p><p>This article shows how design space exploration can be realized through high-level synthesis. It presents a case study of a hardware implementation of the Advanced Encryption Standard (AES) Rijndael algorithm. Star...
 
Distributed Simulation of AADL Specifications in a Polychronous Model of Computation
Found in: Embedded Software and Systems, Second International Conference on
By Yue Ma, Jean-Pierre Talpin, Sandeep K. Shukla, Thierry Gautier
Issue Date:May 2009
pp. 607-614
Architecture Analysis and Design Language (AADL) is used to describe the hardware and software architectures of embedded applications at the system level. The implementation of such systems is often distributed across asynchronous communication infrastruct...
 
Power estimation methodology for a high-level synthesis framework
Found in: Quality Electronic Design, International Symposium on
By Sumit Ahuja, Deepak A. Mathaikutty, Gaurav Singh, Joe Stetzer, Sandeep K. Shukla, Ajit Dingankar
Issue Date:March 2009
pp. 541-546
As adoption of system-level hardware design is increasing in industry and academia, accurate power estimation at this level is becoming important. In this paper, we present a system-level power estimation methodology, which is based on a high-level synthes...
 
Type Inference for IP Composition
Found in: Formal Methods and Models for Co-Design, ACM/IEEE International Conference on
By Deepak A. Mathaikutty, Sandeep K. Shukla
Issue Date:June 2007
pp. 61-70
Type inference and type matching algorithms in the context of a component composition framework are described in this paper. These algorithms facilitate automatic construction of system models from existing SystemC IPs. The approach uses a component compos...
 
Deep vs. Shallow, Kernel vs. Language--What is Better for Heterogeneous Modeling in SystemC?
Found in: Microprocessor Test and Verification, International Workshop on
By Hiren D. Patel, Sandeep K. Shukla
Issue Date:December 2006
pp. 68-75
It is common for large designs to have heterogeneous components interacting with each other. These components often follow a particular model of computation such as controllers modeled using state machines, signal processing filters modeled as data flow an...
 
Automated Extraction of Structural Information from SystemC-based IP for Validation
Found in: Microprocessor Test and Verification, International Workshop on
By David Berner, Hiren D. Patel, Deepak A. Mathaikutty, Sandeep K. Shukla
Issue Date:November 2005
pp. 99-104
The increasing complexity and size of system level design models introduces a difficult challenge for validating them. Hence, in most industries, design validation takes a large percentage of the overall design time. In efforts to alleviate this problem, w...
 
Faster Software Synthesis Using Actor Elimination Techniques for Polychronous Formalism
Found in: Application of Concurrency to System Design, International Conference on
By Bijoy A. Jose, Jason Pribble, Sandeep K. Shukla
Issue Date:June 2010
pp. 147-156
A visual polychronous formalism called Multi-Rate Instantaneous Channel Connected Data Flow (MRICDF)was developed in [1]. In [2], a visual environment called EmCodeSyn was introduced which performs software synthesis from MRICDF models. The synthesis techn...
 
The Model Checking View to Clock Gating and Operand Isolation
Found in: Application of Concurrency to System Design, International Conference on
By Jens Brandt, Klaus Schneider, Sumit Ahuja, Sandeep K. Shukla
Issue Date:June 2010
pp. 181-190
Clock gating and operand isolation are two techniques to reduce the power consumption in state-of-the-art hardware designs. Both approaches basically follow a two-step procedure: first, they statically analyze a hardware circuit to determine irrelevant com...
 
Towards a Heterogeneous Simulation Kernel for System Level Models: A SystemC Kernel for Synchronous Data Flow Models
Found in: VLSI, IEEE Computer Society Annual Symposium on
By Hiren D. Patel, Sandeep K. Shukla
Issue Date:February 2004
pp. 241
As SystemC gains popularity as a modeling language of choice for system-on-chip (SOC) designs, heterogeneous modeling in SystemC and efficient simulation become increasingly important. However, in the current reference implementation, all SystemC models ar...
   
Panel Summaries
Found in: IEEE Design and Test of Computers
By Hans-Joachim Wunderlich, Sandeep K. Shukla
Issue Date:January 2004
pp. 65-66
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Evaluating the Reliability of Defect-Tolerant Architectures for Nanotechnology with Probabilistic Model Checking
Found in: VLSI Design, International Conference on
By Gethin Norman, David Parker, Marta Kwiatkowska, Sandeep K. Shukla
Issue Date:January 2004
pp. 907
As we move from deep submicron technology to nanotechnology for device manufacture, the need for defect-tolerant architectures is gaining importance. This is because, at the nanoscale, devices will be prone to errors due to manufacturing defects, ageing, a...
   
Formal Methods for Dynamic Power Management
Found in: Computer-Aided Design, International Conference on
By Rajesh K. Gupta, Sandy Irani, Sandeep K. Shukla
Issue Date:November 2003
pp. 874
Dynamic Power Management or DPM refers to the problem of judicious application of various low power techniques based on runtime conditions in an embedded system to minimize the total energy consumption. To be effective, often such decisions take into accou...
   
Optimization of Latency Insensitive Systems through Back Pressure Minimization
Found in: IEEE Transactions on Computers
By Bin Xue,Sandeep K. Shukla,S.S. Ravi
Issue Date:December 2013
pp. 1
In this paper, we propose an LIS design optimization algorithm which computes a minimum set of back pressure arcs required between SCCs. We model an LIS by a partial back pressure graph (PBPG) and show that the boundedness of a PBPG can be verified by chec...
 
Accelerating SystemC simulations using GPUs
Found in: 2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)
By Mahesh Nanjundappa,Anirudh Kaushik,Hiren D. Patel,Sandeep K. Shukla
Issue Date:November 2012
pp. 132-139
Recent developments in graphics processing unit (GPU) technology has invigorated an interest in using GPUs for accelerating the simulation of SystemC models. SystemC is extensively used for design space exploration, and early performance analysis of hardwa...
   
Efficient simulation of synthesis-oriented system level designs
Found in: Proceedings of the 15th international symposium on System Synthesis (ISSS '02)
By Nick Savoiu, Rajesh K. Gupta, Sandeep K. Shukla
Issue Date:October 2002
pp. 168-173
Modeling for synthesis and modeling for simulation seem to be two competing goals in the context of C++-based modeling frameworks. One of the reasons is while most hardware systems have some inherent parallelism efficiently expressing it depends on whether...
     
Editorial: Embedded systems -- more than methodology
Found in: ACM Transactions on Embedded Computing Systems (TECS)
By Sandeep K. Shukla
Issue Date:March 2014
pp. 1-2
With increasing application complexity and improvements in process technology, Chip MultiProcessors (CMPs) with tens to hundreds of cores on a chip are becoming a reality. Networks-on-Chip (NoCs) have emerged as scalable communication fabrics that can supp...
     
Editorial: Embedded everywhere for everyone
Found in: ACM Transactions on Embedded Computing Systems (TECS)
By Sandeep K. Shukla
Issue Date:February 2014
pp. 1-2
Phase Change RAM (PRAM) is a candidate to replace DRAM main memory due to its low idle power consumption and high scalability. However, its latency and endurance have generated problems in fulfilling its main memory role. The latency can be treated with a ...
     
Translating concurrent action oriented specifications to synchronous guarded actions
Found in: Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems (LCTES '10)
By Jens Brandt, Klaus Schneider, Sandeep K. Shukla
Issue Date:April 2010
pp. 4.6-4.16
Concurrent Action-Oriented Specifications (CAOS) model the be- havior of a synchronous hardware circuit as asynchronous guarded actions at an abstraction level higher than the Register Transfer Level (RTL). Previous approaches always considered the compila...
     
Model-driven validation of SystemC designs
Found in: Proceedings of the 44th annual conference on Design automation (DAC '07)
By Hiren D. Patel, Sandeep K. Shukla
Issue Date:June 2007
pp. 29-34
Functional test generation for dynamic validation of current system level designs is a challenging task. Manual test writing or automated random test generation techniques are often used for such validation practices. However, directing tests to particular...
     
Design fault directed test generation for microprocessor validation
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '07)
By Ajit Dingankar, David Lilja, Deepak A. Mathaikutty, Sandeep K. Shukla, Sreekumar V. Kodakara
Issue Date:April 2007
pp. 761-766
Functional validation of modern microprocessors is an important and complex problem. One of the problems in functional validation is the generation of test cases that has higher potential to find faults in the design. We propose a model based test generati...
     
Tackling an abstraction gap: co-simulating SystemC DE with bluespec ESL
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '07)
By Hiren D. Patel, Sandeep K. Shukla
Issue Date:April 2007
pp. 279-284
The growing SystemC community for system level design exploration is a result of SystemC's capability of modeling at RTL and above RTL abstraction levels. However, managing shared state concurrency using multi-threading in large SystemC models is error pro...
     
XFM: An incremental methodology for developing formal models
Found in: ACM Transactions on Design Automation of Electronic Systems (TODAES)
By David Berner, Deepak A. Mathaikutty, Sandeep K. Shukla, Syed M. Suhaib
Issue Date:October 2005
pp. 589-609
We present an agile formal methodology named eXtreme Formal Modeling (XFM), based on Extreme Programming (XP) concepts to construct abstract models from natural language specifications of complex systems. In particular, we focus on Prescriptive Formal Mode...
     
Guest editorial: Special issue on models and methodologies for co-design of embedded systems
Found in: ACM Transactions on Embedded Computing Systems (TECS)
By Jean-Pierre Talpin, Sandeep K. Shukla
Issue Date:May 2005
pp. 225-227
This special issue is based on innovative ideas presented and discussed during the first ACM/IEEE Conference on Formal Methods and Models for Co-Design (MEMOCODE) held at Mont Saint Michel in France during the summer of 2003. Selected papers from the confe...
     
I/O automata based verification of finite state distributed systems: complexity issues
Found in: Proceedings of the fifteenth annual ACM symposium on Principles of distributed computing (PODC '96)
By Daniel J. Rosenkrantz, Harry B. Hunt, Richard E. Stearns, S. S. Ravi, Sandeep K. Shukla
Issue Date:May 1996
pp. 122
In [4] a randomized algorithm for mutual exclusion with bounded waiting, employing a logarithmic sized shared variable, was given. Saias and Lynch [5] pointed out that the adversary scheduler postulated in the above paper can observe the behavior of proces...
     
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