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Displaying 1-24 out of 24 total
System-on-Chip Oriented Fault-Tolerant Sequential Systems Implementation Methodology
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By S. Pontarelli, G.C. Cardarilli, A. Malvoni, M. Ottavi, M. Re, A. Salsano
Issue Date:October 2001
pp. 0455
This paper presents a design methodology for fault tolerant sequential systems implemented on System on Chip (SoC). In the paper, as an example, a complex fault tolerant finite state machine has been mapped on the FPGA contained in the SoC. The fault ident...
 
Design of a Totally Self Checking Signature Analysis Checker for Finite State Machines
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By M. Ottavi, G. C. Cardarilli, D. Cellitti, S. Pontarelli, M. Re, A. Salsano
Issue Date:October 2001
pp. 0403
This paper describes the design of a totally self-checking signature analysis checker to be used to implement self-checking finite state machines. The application of the signature analysis method is studied taking into account trade off criteria concerning...
 
High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies
Found in: 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
By C. Bolchini,A. Miele,C. Sandionigi,M. Ottavi,S. Pontarelli,A. Salsano,C. Metra,M. Omana,D. Rossi,M. Sonza Reorda,L. Sterpone,M. Violante,S. Gerardin,M. Bagatin,A. Paccagnella
Issue Date:October 2012
pp. 121-125
While the shrinking of minimum dimensions of integrated circuits till tenths of nanometers allows the integration of millions of gates on the single chip, it also implies the growth of the importance of effects that could reduce the reliability of circuits...
 
Data Integrity Evaluations of Reed Solomon Codes for Storage Systems
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By G. C. Cardarilli, M. Ottavi, S. Pontarelli, M. Re, A. Salsano
Issue Date:October 2004
pp. 158-164
This paper introduces a very flexible approach for the evaluation of Bit Error Rate (BER) attainable on storage systems which use Reed Solomon codes. These evaluations are based on the use of a Markov model to evaluate the probabilities of having an uncorr...
 
Reliability Evaluation of Repairable/Reconfigurable FPGAs
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By S. Pontarelli, M. Ottavi, V. Vankamamidi, A. Salsano, F. Lombardi
Issue Date:October 2006
pp. 227-235
Many techniques have been proposed in the technical literature for repairing FPGAs when affected by permanent faults. Almost all of these works exploit the dynamic reconfiguration FPGA; a subset of the available resources is used as spares for replacing th...
 
Design and Evaluation of a Hardware on-line Program-Flow Checker for Embedded Microcontrollers
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By M. Ottavi, S. Pontarelli, A. Leandri, A. Salsano
Issue Date:October 2006
pp. 371-379
This paper investigates the effects of a class of transient faults, the so-called Single Event Upsets, on the execution of programs in typical microcontroller architecture as can be found on a system on chip for embedded applications. It is observed that t...
 
Novel designs for thermally robust coplanar crossing in QCA
Found in: Design, Automation and Test in Europe Conference and Exhibition
By S. Bhanja, M. Ottavi, F. Lombardi, S. Pontarelli
Issue Date:March 2006
pp. 170
In this paper, different circuit arrangements of quantum-dot cellular automata (QCA) are proposed for the so-called coplanar crossing. These arrangements exploit the majority voting properties of QCA to allow a robust crossing of wires on the Cartesian pla...
 
Optimization of Self Checking FIR filters by means of Fault Injection Analysis
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By S. Pontarelli, L. Sterpone, G.C. Cardarilli, M. Re, M. Sonza Reorda, A. Salsano, M. Violante
Issue Date:September 2007
pp. 96-104
In this paper the design of a FIR filter with self checking capabilities based on the residue checking is analyzed. Usually the set of residues used to check the consistency of the results of the FIR filter are based of theoretic considerations about the d...
 
Localization of Faults in Radix-n Signed Digit Adders
Found in: On-Line Testing Symposium, IEEE International
By G.C. Cardarilli, M. Ottavi, S. Pontarelli,, M. Re, A. Salsano
Issue Date:July 2006
pp. 178-180
It is widely known that a adder can be checked by using check symbols that are residues of the numbers modulo some base. This paper extends this characteristic to a radix r Signed Digit (SD) representation. The confinement of the carry operation can also b...
 
A Novel Error Detection and Correction Technique for RNS Based FIR Filters
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By S. Pontarelli, G.C. Cardarilli, M. Re, A. Salsano
Issue Date:October 2008
pp. 436-444
n this paper a novel technique for detecting and correcting errors in the RNS representation is presented. It is based on the selection of a particular subset of the legitimate range of the RNS representation characterized by the property that each element...
 
On the Analysis of Reed Solomon Coding for Resilience to Transient/Permanent Faults in Highly Reliable Memories
Found in: Design, Automation and Test in Europe Conference and Exhibition
By L. Schiano, M. Ottavi, F. Lombardi, S. Pontarelli, A. Salsano
Issue Date:March 2005
pp. 580-585
Single Event Upsets (SEU) as well as permanent faults can significantly affect the correct on-line operation of digital systems, such as memories and microprocessors; a memory can be made resilient to permanent and transient faults by using modular redunda...
 
A Signed Digit Adder with Error Correction and Graceful Degradation Capabilities
Found in: On-Line Testing Symposium, IEEE International
By G. C. Cardarilli, M. Ottavi, S. Pontarelli, M. Re, A. Salsano
Issue Date:July 2004
pp. 141
This paper proposes a methodology to obtain fault localization and graceful degradation of a self-checking adder based on signed digit representation. The main idea underlying the paper is to exploit the fact that in signed digit arithmetic the carry opera...
 
Bit Flip Injection in Processor-Based Architectures: A Case Study
Found in: On-Line Testing Workshop, IEEE International
By G. C. Cardarilli, F. Kaddour, A. Leandri, M. Ottavi, S. Pontarelli, R. Velazco
Issue Date:July 2002
pp. 117
This paper presents the principles of two different approaches for the study of the effect of transient bit flips on the behavior of processor-based digital architectures: one of them based on the on-line
 
Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders
Found in: On-Line Testing Symposium, IEEE International
By S. Pontarelli, L. Sterpone, G.C. Cardarilli, M. Re, M. Sonza Reorda, A. Salsano, M. Violante
Issue Date:July 2007
pp. 194-196
This paper shows how the use of exhaustive fault injection campaigns in conjunction with the analysis of the property of a circuit, allows to improve the efficiency of the checker of self checking circuits. Experimental results coming from fault injection ...
 
A Self Checking Reed Solomon Encoder: Design and Analysis
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By G.C. Cardarilli, S. Pontarelli, M. Re, A. Salsano
Issue Date:October 2005
pp. 111-119
<p>Reed Solomon codes are widely used to identify and correct data errors in transmission and storage systems. Due to the vital importance of these blocks, a very important research topic is the study of the effects of faults on their behavior. The p...
 
Error Detection and Correction in Content Addressable Memories
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By S. Pontarelli, M. Ottavi, A. Salsano
Issue Date:October 2010
pp. 420-428
A Content Addressable Memory (CAM) is an SRAM based memory which can be accessed in parallel in order to search for a given search word, providing as result the address of the matching data. The use of CAM is widespread in many applications ranging from th...
 
Error Correction Codes for SEU and SEFI Tolerant Memory Systems
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By S. Pontarelli, G.C. Cardarilli, M. Re, A. Salsano
Issue Date:October 2009
pp. 425-430
In this paper a modification of the Hsiao SEC-DED (Single Error Correction, Double Error Detection) code is presented. The proposed code is still a SEC-DED code, but it is also able to correct a byte erasure. This code has been developed to protect the mem...
 
Totally Fault Tolerant RNS Based FIR Filters
Found in: On-Line Testing Symposium, IEEE International
By S. Pontarelli, G.C. Cardarilli, M. Re, A. Salsano
Issue Date:July 2008
pp. 192-194
In this paper, the design of a Finite Impulse Response (FIR) filter with fault tolerant capabilities based on the residue number system is analyzed. Differently from other approaches that use RNS, the filter implementation is fault tolerant not only with r...
 
FPGA oriented design of parity sharing RS codecs
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By G.C. Cardarilli, S. Pontarelli, M. Re, A. Salsano
Issue Date:October 2005
pp. 259-265
<p>Reed Solomon codes are widely used to protect the information from errors in transmission and storage systems. RS codes rely on arithmetic in finite, or Galois fields. Most of the RS coders are based on the field GF(28), using a byte as a symbol a...
 
Design of a Self Checking Reed Solomon Encoder
Found in: On-Line Testing Symposium, IEEE International
By G. C. Cardarilli, S. Pontarelli, M. Re, A. Salsano
Issue Date:July 2005
pp. 201-202
In this paper, an innovative self-checking Reed Solomon encoder architecture is described. The presented architecture exploits some properties of the arithmetic operations in GF(2s) related to the parity of the binary representation of the field elements. ...
   
Evaluating the Data Integrity of Memory Systems by Configurable Markov Models
Found in: VLSI, IEEE Computer Society Annual Symposium on
By M. Ottavi, L. Schiano, F. Lombardi, S. Pontarelli, G. C. Cardarilli
Issue Date:May 2005
pp. 257-259
In this paper, a novel method for the evaluation of the Bit Error Rate (BER) as measure for assessing data integrity in memory systems is proposed; such method improves modeling by introducing configurability features in the Markov chains to account for en...
 
Error detection in addition chain based ECC Point Multiplication
Found in: On-Line Testing Symposium, IEEE International
By S. Pontarelli, G.C. Cardarilli, M. Re, A. Salsano
Issue Date:June 2009
pp. 192-194
In this paper the problem of error detection in elliptic curve point multiplication is faced. Elliptic Curve Point Multiplication is often used to design cryptographic algorithms that use fewer bits than other methods with the same security level. One of t...
 
Feedback based droop mitigation
Found in: 2011 Design, Automation & Test in Europe
By S Pontarelli,M Ottavi,A Salsano,K Zarrineh
Issue Date:March 2011
pp. 1-4
A strong dl/dt event in a VLSI circuit can induce a temporary voltage drop and consequent malfunctioning of logic as for instance failing speed paths. This event, called power droop, usually manifests itself in at-speed scan test where a surge in switching...
   
Error Detection in Signed Digit Arithmetic Circuit with Parity Checker
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By G.C. Cardarilli, M. Ottavi, S. Pontarelli, M. Re, A. Salsano
Issue Date:November 2003
pp. 401
This paper proposes a methodology for the development of simple arithmetic self-checking circuits using Signed Digit representation. In particular, the architecture of an adder is reported and its self-checking capability with respect to the stuck-at fault...
 
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