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Displaying 1-16 out of 16 total
Low-capture-power test generation for scan-based at-speed testing
Found in: Test Conference, International
By Y. Yamashita, S. Morishima, S. Kajihara, Laung-Terng Wang, K.K. Saluja, K. Kinoshita
Issue Date:November 2005
pp. 10 pp.-1028
Scan-based at-speed testing is a key technology to guarantee timing-related test quality in the deep submicron era. However, its applicability is being severely challenged since significant yield loss may occur from circuit malfunction due to excessive IR ...
Invisible delay quality - SDQM model lights up what could not be seen
Found in: Test Conference, International
By Y. Sato, S. Hamada, T. Maeda, A. Takatori, Y. Nozuyama, S. Kajihara
Issue Date:November 2005
pp. 9 pp.-1210
The quality of delay testing focused on small delay defects is not clear when traditional fault models are used. We therefore evaluated the feasibility of using the statistical delay quality model (SDQM) - which reflects fabrication process quality, design...
Test sequence compaction by reduced scan shift and retiming
Found in: Asian Test Symposium
By Y. Higami, S. Kajihara, K. Kinoshita
Issue Date:November 1995
pp. 169
This paper presents a method to compact test sequences for full scan designed circuits by using the reduced scan shift and the retiming. The reduced scan shift, which we previously proposed, can compact test sequences by omitting unnecessary scan shifts. I...
Compact test generation for bridging faults under I/sub DDQ/ testing
Found in: VLSI Test Symposium, IEEE
By R.S. Reddy, I. Pomeranz, S.M. Reddy, S. Kajihara
Issue Date:May 1995
pp. 0310
Abstract: We propose a procedure to generate compact test sets for bridging faults under I/sub DDQ/ testing. Several techniques are employed to achieve compact test sets. Heuristics developed for stuck-at faults are shown to be effective in this context. T...
A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths
Found in: VLSI Design, International Conference on
By S. Kajihara, K. Kinoshita, I. Pomeranz, S.M. Reddy
Issue Date:January 1997
pp. 82
It has been shown previously that a logic circuit often contains a large number of logical paths that need not be tested to verify the timing behavior of the circuit, if the other paths are robustly tested. These paths are called robust dependent. A subset...
On pinpoint capture power management in at-speed scan test generation
Found in: 2012 IEEE International Test Conference (ITC)
By X. Wen,Y. Nishida,K. Miyase,S. Kajihara,P. Girard,M. Tehranipoor,L.-T. Wang
Issue Date:November 2012
pp. 1-10
This paper proposes a novel scheme to manage capture power in a pinpoint manner for achieving guaranteed capture power safety, improved small-delay test capability, and minimal test cost impact in at-speed scan test generation. First, switching activity ar...
Resynthesis for sequential circuits designed with a specified initial state
Found in: VLSI Test Symposium, IEEE
By H. Yotsuyanagi, S. Kajihara, K. Kinoshita
Issue Date:May 1995
pp. 0152
Abstract: This paper presents a retiming and redundancy removal method for a sequential circuit with a specified initial state so that the resynthesized circuit has a state corresponding to the initial state and gives same behavior for any input sequences ...
Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling
Found in: Asian Test Symposium
By K. Miyase,Y. Uchinodan,K. Enokimoto,Y. Yamato,X. Wen,S. Kajihara,F. Wu,L. Dilillo,A. Bosio,P. Girard,A. Virazel
Issue Date:November 2011
pp. 90-95
It has become necessary to reduce power during LSI testing. Particularly, during at-speed testing, excessive power consumed during the Launch-To-Capture (LTC) cycle causes serious issues that may lead to the overkill of defect-free logic ICs. Many successf...
On the effects of test compaction on defect coverage
Found in: VLSI Test Symposium, IEEE
By S.M. Reddy, I. Pomeranz, S. Kajihara
Issue Date:May 1996
pp. 430
We study the effects of test compaction on the defect coverage of test sets for modeled faults. Using a framework proposed earlier, defects are represented by surrogate faults. Within this framework, we show that the defect coverage does not have to be sac...
CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing
Found in: Asian Test Symposium
By H. Furukawa, X. Wen, K. Miyase, Y. Yamato, S. Kajihara, P. Girard, L.-T. Wang, M. Tehranipoor
Issue Date:November 2008
pp. 397-402
At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switc...
LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing
Found in: IEEE Design & Test of Computers
By Y. Yamato,X. Wen,M. Kochte,K. Miyase,S. Kajihara,L. Wang
Issue Date:October 2012
pp. 1
Moving further into the deep-submicron era, the problem of test-induced yield loss due to high power consumption has increasingly worsened. One of the major causes of this problem is shift timing failure, which arises from excessive switching activity in t...
A Capture-Safe Test Generation Scheme for At-Speed Scan Testing
Found in: European Test Symposium, IEEE
By X. Wen, K. Miyase, S. Kajihara, H. Furukawa, Y. Yamato, A. Takashima, K. Noda, H. Ito, K. Hatayama, T. Aikyo, K. K. Saluja
Issue Date:May 2008
pp. 55-60
Capture-safety, defined as the avoidance of any timing error due to unduly high launch switching activity in capture mode during at-speed scan testing, is critical for avoiding test- induced yield loss. Although point techniques are available for reducing ...
Enhanced untestable path analysis using edge graphs
Found in: Asian Test Symposium
By S. Kajihara, T. Shimono, I. Pomeranz, S.M. Reddy
Issue Date:December 2000
pp. 139
Logic circuits may have large numbers of untestable paths. Therefore, it is important for path delay fault testing to identify untestable paths prior to test generation. An earlier method, called partial path sensitization, was able to identify large numbe...
On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST
Found in: 2013 22nd Asian Test Symposium (ATS)
By A. Tomita,X. Wen,Y. Sato,S. Kajihara,P. Girard,M. Tehranipoor,L.T. Wang
Issue Date:November 2013
pp. 19-24
The applicability of at-speed scan-based logic built-in self-test (BIST) is being severely challenged by excessive capture power that may cause erroneous test responses for good chips. Different from conventional low-power BIST, this paper is the first tha...
Transition-Time-Relation based capture-safety checking for at-speed scan test generation
Found in: 2011 Design, Automation & Test in Europe
By K Miyase,X Wen,M Aso,H Furukawa,Y Yamato,S Kajihara
Issue Date:March 2011
pp. 1-4
Excessive capture power in at-speed scan testing may cause timing failures, resulting in test-induced yield loss. This has made capture-safety checking mandatory for test vectors. This paper presents a novel metric, called the TTR (Transition-Time-Relation...
An Efficient Procedure for Obtaining Implication Relations and Its Application to Redundancy Identification
Found in: Asian Test Symposium
By H. Ichihara, S. Kajihara, K. Kinoshita
Issue Date:December 1998
pp. 58
The procedure used in static learning extracts implication relations of the logic circuit. The number of extracted implication relations depends on the order of signal lines processed. In this paper we propose an efficient method to extract implication rel...