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Displaying 1-50 out of 67 total
Design methods for Wireless Sensor Network Building Energy Monitoring Systems
Found in: Local Computer Networks, Annual IEEE Conference on
By Inkeun Cho,Chung-Ching Shen,Siddharth Potbhare,Shuvra S. Bhattacharyya,Neil Goldsman
Issue Date:October 2011
pp. 974-981
In this paper, we present a new energy analysis method for evaluating energy consumption of embedded sensor nodes at the application level and the network level. Then we apply the proposed energy analysis method to develop new energy management schemes in ...
 
Modeling and optimization of dynamic signal processing in resource-aware sensor networks
Found in: Advanced Video and Signal Based Surveillance, IEEE Conference on
By S. S. Bhattacharyya,W. Plishker,N. Sane, Chung-Ching Shen, Hsiang-Huang Wu
Issue Date:September 2011
pp. 449-454
Sensor node processing in resource-aware sensor networks is often critically dependent on dynamic signal processing functionality - i.e., signal processing functionality in which computational structure must be dynamically assessed and adapted based on tim...
 
A design tool for efficient mapping of multimedia applications onto heterogeneous platforms
Found in: Multimedia and Expo, IEEE International Conference on
By Chung-Ching Shen, Hsiang-Huang Wu,Nimish Sane,William Plishker,Shuvra S. Bhattacharyya
Issue Date:July 2011
pp. 1-6
Development of multimedia systems on heterogeneous platforms is a challenging task with existing design tools due to a lack of rigorous integration between high level abstract modeling, and low level synthesis and analysis. In this paper, we present a new ...
 
A Model-Based Schedule Representation for Heterogeneous Mapping of Dataflow Graphs
Found in: Parallel and Distributed Processing Workshops and PhD Forum, 2011 IEEE International Symposium on
By Hsiang-Huang Wu,Chung-Ching Shen,Nimish Sane,William Plishker,Shuvra S. Bhattacharyya
Issue Date:May 2011
pp. 70-81
Dataflow-based application specifications are widely used in model-based design methodologies for signal processing systems. In this paper, we develop a new model called the dataflow schedule graph (DSG) for representing a broad class of dataflow graph sch...
 
High-Performance Buffer Mapping to Exploit DRAM Concurrency in Multiprocessor DSP Systems
Found in: Rapid System Prototyping, IEEE International Workshop on
By Dongwon Lee, Shuvra S. Bhattacharyya, Wayne Wolf
Issue Date:June 2009
pp. 137-144
Design methodologies and tools based on the synchronous dataflow (SDF) model of computation have proven useful for rapid prototyping and implementation of digital signal processing (DSP) applications on multiprocessor systems. One significant problem that ...
 
Functional DIF for Rapid Prototyping
Found in: Rapid System Prototyping, IEEE International Workshop on
By William Plishker, Nimish Sane, Mary Kiemb, Kapil Anand, Shuvra S. Bhattacharyya
Issue Date:June 2008
pp. 17-23
Dataflow formalisms have provided designers of digital signal processing systems with optimizations and guarantees to arrive at quality prototypes quickly. As system complexity increases, designers are expressing more types of behavior in dataflow language...
 
Design and optimization of a distributed, embedded speech recognition system
Found in: Parallel and Distributed Processing Symposium, International
By Chung-Ching Shen, William Plishker, Shuvra S. Bhattacharyya
Issue Date:April 2008
pp. 1-8
In this paper, we present the design and implementation of a distributed sensor network application for embedded, isolated-word, real-time speech recognition. In our system design, we adopt a parameterized-data-flow-based modeling approach to model the fun...
 
An Energy-Driven Design Methodology for Distributing DSP Applications across Wireless Sensor Networks
Found in: Real-Time Systems Symposium, IEEE International
By Chung-Ching Shen, William Plishker, Shuvra S. Bhattacharyya, Neil Goldsman
Issue Date:December 2007
pp. 214-226
Wireless sensor network (WSN) applications have been studied extensively in recent years. Such applica- tions involve resource-limited embedded sensor nodes that have small size and low power requirements. Based on the need for extended network lifetimes i...
 
Contention-Conscious Transaction Ordering in Embedded Multiprocessors
Found in: Application-Specific Systems, Architectures and Processors, IEEE International Conference on
By Mukul Khandelia, Shuvra S. Bhattacharyya
Issue Date:July 2000
pp. 276
This paper explores the problem of efficiently ordering interprocessor communication operations in statically scheduled multiprocessors for iterative dataflow graphs. In digital signal processing applications, the throughput of the system is significantly ...
 
A Class of End-to-End Congestion Control Algorithms for the Internet
Found in: Network Protocols, IEEE International Conference on
By S. Golestani, S. Bhattacharyya
Issue Date:October 1998
pp. 0137
No summary available.
 
Latency-constrained Resynchronization for Multiprocessor DSP Implementation
Found in: Application-Specific Systems, Architectures and Processors, IEEE International Conference on
By S. S. Bhattacharyya, S. Sriram, E. A. Lee
Issue Date:August 1996
pp. 365
Resynchronization is a post-optimization for static multiprocessor schedules in which extraneous synchronization operations are introduced in such a way that the number of original synchronizations that consequently become redundant significant exceeds the...
 
A Buffer Merging Technique for Reducing Memory Requirements of Synchronous Dataflow Specifications
Found in: System Synthesis, International Symposium on
By Praveen K. Murthy, Shuvra S. Bhattacharyya
Issue Date:November 1999
pp. 78
Synchronous Dataflow, a subset of dataflow, has proven to be a good match for specifying DSP programs. Because of the limited amount of memory in embedded DSPs, a key problem during software synthesis from SDF specifications is the minimization of the memo...
 
Self-Timed Resynchronization: A Post-Optimization for Static Multiprocessor Schedules
Found in: Parallel Processing Symposium, International
By Shuvra S. Bhattacharyya, Sundararajan Sriram, Edward A. Lee
Issue Date:April 1996
pp. 199
In a shared-memory multiprocessor system, it is possible that certain synchronization operations are redundant - that is, their corresponding sequencing requirements are enforced completely by other synchronizations in the system - and can be eliminated wi...
 
Shared Memory Implementations of Synchronous Dataflow Specifications
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Praveen K. Murthy, Shuvra S. Bhattacharyya
Issue Date:March 2000
pp. 404
There has been a proliferation of block-diagram environments for specifying and prototyping DSP systems. These include tools from academia like Ptolemy [3], and GRAPE [7], and commercial tools like SPW from Cadence Design Systems, Cossap from Synopsys, and...
 
Partial Expansion Graphs: Exposing Parallelism and Dynamic Scheduling Opportunities for DSP Applications
Found in: 2012 IEEE 23rd International Conference on Application-specific Systems, Architectures and Processors (ASAP)
By George F. Zaki,William Plishker,Shuvra S. Bhattacharyya,Frank Fruth
Issue Date:July 2012
pp. 86-93
Emerging Digital Signal Processing (DSP) algorithms and wireless communications protocols require dynamicadaptation and online reconfiguration for the implementedsystems at runtime. In this paper, we introduce the conceptof Partial Expansion Graphs (PEGs) ...
 
An Optimized Message Passing Framework for Parallel Implementation of Signal Processing Applications
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Sankalita Saha, Jason Schlessman, Sebastian Puthenpurayil, Shuvra S. Bhattacharyya, Wayne Wolf
Issue Date:March 2008
pp. 1220-1225
Novel reconfigurable computing platforms enable efficient realizations of complex signal processing applications by allowing exploitation of parallelization resulting in high throughput in a cost-efficient way. However, the design of such systems poses var...
 
Interconnect Synthesis for Systems on Chip
Found in: System-on-Chip for Real-Time Applications, International Workshop on
By Neal K. Bambha, Shuvra S. Bhattacharyya
Issue Date:July 2004
pp. 263-268
We describe an algorithm for performing a joint scheduling/interconnect synthesis optimization for System-on-Chip (SoC) architectures. The algorithm is able to account for different distributions of long vs. short interconnect routes in an architecture. It...
 
A Hierarchical Multiprocessor Scheduling System for DSP Applications
Found in: Asilomar Conference on Signals, Systems and Computers
By Jose Luis Pino, Edward A. Lee, Shuvra S. Bhattacharyya
Issue Date:November 1995
pp. 122
This paper discusses a hierarchical scheduling framework which reduces the complexity of scheduling synchronous datajow (SDF) graphs onto multiple processors. The core of this framework is a clustering algorithm that decreases the number of nodes before ex...
 
An architectural level design methodology for embedded face detection
Found in: Hardware/software codesign and system synthesis, International conference on
By R. Chellappa, S. S. Bhattacharyya, S. Saha, W. Wolf, G. Aggarwal, J. Schlessman, V. Kianzad
Issue Date:September 2005
pp. 136-141
Face detection and recognition research has attracted great attention in recent years. Automatic face detection has great potential in a large array of application areas, including banking and security system access control, video surveillance, and multime...
 
A Joint Power/Performance Optimization Algorithm for Multiprocessor Systems Using a Period Graph Construct
Found in: System Synthesis, International Symposium on
By Neal K. Bambha, Shuvra S. Bhattacharyya
Issue Date:September 2000
pp. 91
A critical challenge in synthesis techniques for iterative applications is the efficient analysis of performance in the presence of communication resource contention. To address this challenge, we introduce the concept of the period graph. The period graph...
 
A rapid prototyping methodology for application-specific sensor networks
Found in: Application-Specific Systems, Architectures and Processors, IEEE International Conference on
By Chung-Ching Shen, Celine Badr, Kamiar Kordari, Shuvra S. Bhattacharyya, Gilmer L. Blankenship, Neil Goldsman
Issue Date:July 2007
pp. 130-135
Wireless sensor network systems depend on many interrelated system parameters. The associated design space is vast, and effective optimization in this space is challenging. In this paper, we introduce a system-level design methodology to find efficient con...
 
The pipeline decomposition tree:: an analysis tool for multiprocessor implementation of image processing applications
Found in: Hardware/software codesign and system synthesis, International conference on
By Shuvra S. Bhattacharyya, Dong-Ik Ko
Issue Date:October 2006
pp. 52-57
Modern embedded systems for image processing involve increasingly complex levels of functionality under real-time and resource-related constraints. As this complexity increases, the application of single-chip multiprocessor technology is attractive. To add...
 
Porting DSP Applications across Design Tools Using the Dataflow Interchange Format
Found in: Rapid System Prototyping, IEEE International Workshop on
By Chia-Jui Hsu, Shuvra S. Bhattacharyya
Issue Date:June 2005
pp. 40-46
Modeling DSP applications through coarse-grain dataflow graphs is popular in the DSP design community, and a growing set of rapid prototyping tools support such dataflow semantics. Since different tools may be suitable for different phases or generations o...
 
Computer Vision on FPGAs: Design Methodology and its Application to Gesture Recognition
Found in: Computer Vision and Pattern Recognition Workshop
By Mainak Sen, Ivan Corretjer, Fiorella Haim, Sankalita Saha, Shuvra S. Bhattacharyya, Jason Schlessman, Wayne Wolf
Issue Date:June 2005
pp. 133
<p>In this paper we develop a design methodology for generating efficient, target specific Hardware Description Language (HDL) code from an algorithm through the use of coarse-grain reconfigurable dataflow graphs as a representation to guide the desi...
 
Minimizing Synchronization Overhead in Statically Scheduled Multiprocessor Systems
Found in: Application-Specific Systems, Architectures and Processors, IEEE International Conference on
By Shuvra S. Bhattacharyya, Sundararajan Sriram, Edward A. Lee
Issue Date:July 1995
pp. 298
Synchronization overhead can significantly degrade performance in embedded multiprocessor systems. This paper develops techniques to determine a minimal set of processor synchronizations that are essential for correct execution in an embedded multiprocesso...
 
Real-Time Logic Verification of a Wireless Sensor Network
Found in: Computer Science and Information Engineering, World Congress on
By J. Green, S. Bhattacharyya, B. Panja
Issue Date:April 2009
pp. 269-273
Monitoring and control of systems using a Wireless Sensor Network (WSN) play a significant role in rapid automated response to events. Automation drives the necessity to check the system correctness due to the critical nature of the operations (i.e. milita...
 
Model-Based OpenMP Implementation of a 3D Facial Pose Tracking System
Found in: Parallel Processing Workshops, International Conference on
By Sankalita Saha, Chung-Ching Shen, Chia-Jui Hsu, Gaurav Aggarwal, Ashok Veeraraghavan, Alan Sussman, Shuvra S. Bhattacharyya
Issue Date:August 2006
pp. 66-73
Most image processing applications are characterized by computation-intensive operations, and high memory and performance requirements. Parallelized implementation on shared-memory systems offer an attractive solution to this class of applications. However...
 
Joint Application Mapping/Interconnect Synthesis Techniques for Embedded Chip-Scale Multiprocessors
Found in: IEEE Transactions on Parallel and Distributed Systems
By Neal K. Bambha, Shuvra S. Bhattacharyya
Issue Date:February 2005
pp. 99-112
<p><b>Abstract</b>—As transistor sizes shrink, interconnects represent an increasing bottleneck for chip designers. Several groups are developing new interconnection methods and system architectures to cope with this trend. New architectu...
 
CHARMED: A Multi-Objective Co-Synthesis Framework for Multi-Mode Embedded Systems
Found in: Application-Specific Systems, Architectures and Processors, IEEE International Conference on
By Vida Kianzad, Shuvra S. Bhattacharyya
Issue Date:September 2004
pp. 28-40
In this paper, we present a modular co-synthesis framework called CHARMED that solves the problem of hardware-software co-synthesis of periodic, multi-mode, distributed, embedded systems. In this framework we perform the synthesis under several constraints...
 
Exploring the Probabilistic Design Space of Multimedia Systems
Found in: Rapid System Prototyping, IEEE International Workshop on
By Shaoxiong Hua, Gang Qu, Shuvra S. Bhattacharyya
Issue Date:June 2003
pp. 233
In this paper, we propose the novel concept of probabilistic design for multimedia systems and a methodology to quickly explore such design space at an early design stage. The probabilistic design is motivated by the challenge of how to design, but not ove...
 
Design Considerations for Optically Connected Systems on Chip
Found in: System-on-Chip for Real-Time Applications, International Workshop on
By Neal K. Bambha, Shuvra S. Bhattacharyya, Gary Euliss
Issue Date:July 2003
pp. 299
This paper addresses some fundamental issues relating to the design of systems on chip that utilize optical interconnects. We present an information theoretical model for assessing trade-offs between global and local partitions in these systems, and evalua...
 
Exploiting statically schedulable regions in dataflow programs
Found in: Acoustics, Speech, and Signal Processing, IEEE International Conference on
By Ruirui Gu, Jorn W. Janneck, Mickael Raulet, Shuvra S. Bhattacharyya
Issue Date:April 2009
pp. 565-568
Dataflow descriptions have been used in a wide range of Digital Signal Processing (DSP) applications, such as multi-media processing, and wireless communications. Among various forms of dataflow modeling, Synchronous Dataflow (SDF) is geared towards static...
 
Affine Nested Loop Programs and their Binary Parameterized Dataflow Graph Counterparts
Found in: Application-Specific Systems, Architectures and Processors, IEEE International Conference on
By Ed F. Deprettere, Todor Stefanov, Shuvra S. Bhattacharyya, Mainak Sen
Issue Date:September 2006
pp. 186-190
Parameterized static affine nested loop programs can be automatically converted to input-output equivalent Kahn Process Network specifications. These networks turn out to be close relatives of parameterized cyclo-static dataflow graphs. Token production an...
 
A Component Architecture for FPGA-Based, DSP System Design
Found in: Application-Specific Systems, Architectures and Processors, IEEE International Conference on
By Gary Spivey, Shuvra S. Bhattacharyya, Kazuo Nakajima
Issue Date:July 2002
pp. 41
Introducing FPGA components into DSP system implementations creates an assortment of challenges across system architecture and logic design. Recognizing that some of the greatest challenges occur in the integration of the various components, we have develo...
 
Relocation in Mobile Process-Centered Software Development Environments
Found in: Database and Expert Systems Applications, International Workshop on
By S. Bhattacharyya, L.J. Osterweil
Issue Date:September 2000
pp. 198
The paper demonstrates how analysis of a software development process specification can support effective planning for accommodating mobile users of process centered software development environments. The paper presents a flow graph analysis based approach...
 
Quasi-Static Scheduling of Reconfigurable Dataflow Graphs for DSP Systems
Found in: Rapid System Prototyping, IEEE International Workshop on
By Bishnupriya Bhattacharya, Shuvra S. Bhattacharyya
Issue Date:June 2000
pp. 84
Dataflow programming has proven to be popular for representing applications in rapid prototyping tools for digital signal processing (DSP); however, existing dataflow design tools are limited in their ability to effectively handle dynamic application behav...
 
Energy Reduction Techniques for Multimedia Applications with Tolerance to Deadline Misses
Found in: Design Automation Conference
By Shaoxiong Hua, Gang Qu, Shuvra S. Bhattacharyya
Issue Date:June 2003
pp. 131
Many embedded systems such as PDAs require processing of the given applications with rigid power budget. However, they are able to tolerate occasional failures due to the imperfect human visual/auditory systems. The problem we address in this paper is how ...
 
Java-through-C Compilation: An Enabling Technology for Java in Embedded Systems
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Ankush Varma, Shuvra S. Bhattacharyya
Issue Date:February 2004
pp. 30161
<p>The Java programming language is acheiving greater acceptance in high-end embedded systems such as cellphones and PDAs. However, current embedded implementations of Java impose tight constraints on functionality, while requiring significant storag...
 
3D Exploration of Software Schedules for DSP Algorithms
Found in: Hardware/Software Co-Design, International Workshop on
By J. Teich, E. Zitzler, S. S. Bhattacharyya
Issue Date:May 1999
pp. 168
This paper addresses the problem of exploring tradeoffs between program memory, data memory and execution time requirements (3D) for DSP algorithms specified by data flow graphs. Such an exploration is of utmost importance for being able to analyse the fea...
 
Efficient Techniques for Clustering and Scheduling onto Embedded Multiprocessors
Found in: IEEE Transactions on Parallel and Distributed Systems
By Vida Kianzad, Shuvra S. Bhattacharyya
Issue Date:July 2006
pp. 667-680
<p><b>Abstract</b>—Multiprocessor mapping and scheduling algorithms have been extensively studied over the past few decades and have been tackled from different perspectives. In the late 1980's, the two-step decomposition of scheduling—in...
 
CASPER: An Integrated Energy-Driven Approach for Task Graph Scheduling on Distributed Embedded Systems
Found in: Application-Specific Systems, Architectures and Processors, IEEE International Conference on
By Vida Kianzad, Shuvra S. Bhattacharyya, Gang Qu
Issue Date:July 2005
pp. 191-197
<p>For multiprocessor embedded systems, the dynamic voltage scaling (DVS) technique can be applied to scheduled applications for energy reduction. DVS utilizes slack in the schedule to slow down processes and save energy. Therefore, it is generally b...
 
Guest Editors' Introduction: Taking on the Embedded System Design Challenge
Found in: Computer
By Jörg Henkel, Xiaobo Sharon Hu, Shuvra S. Bhattacharyya
Issue Date:April 2003
pp. 35-37
<p>A new generation of synthesis tools has provided the primary driving force behind the integration of hardware and software components during system design and development.</p>
 
iMASH: interactive mobile application session handoff
Found in: Proceedings of the 1st international conference on Mobile systems, applications and services (MobiSYS '03)
By E. Skow, F. Cheng, G. Glazer, G. Zorpas, J. Lin, M. Varshney, R. Bagrodia, R. Guy, S. Bhattacharyya, S. Gerding, T. Phan, Z. Ji
Issue Date:May 2003
pp. 259-272
Mobile computing research has often focused on untethering an in-use computing device, rather than enabling the mobility of the computation task itself. This paper presents an architecture, implementation, and experimental evidence that together validate a...
     
Hybrid Global/Local Search Strategies for Dynamic Voltage Scaling in Embedded Multiprocessors
Found in: Hardware/Software Co-Design, International Workshop on
By Neal K. Bambha, Shuvra S. Bhattacharyya, Jürgen Teich, Eckart Zitzler
Issue Date:April 2001
pp. 243
In this paper, we explore a hybrid global/local search optimization framework for dynamic voltage scaling in embedded multiprocessor systems. The problem is to find, for a multiprocessor system in which the processors are capable of dynamically varying the...
 
3D exploration of software schedules for DSP algorithms
Found in: Proceedings of the seventh international workshop on Hardware/software codesign (CODES '99)
By E. Zitzler, J. Teich, S. S. Bhattacharyya
Issue Date:March 1999
pp. 168-172
We present a parallel implementation of the Buckshot document clustering algorithm. We demonstrate that this parallel approach is highly efficient both in terms of load balancing and minimization of communication. In a series of experiments using the 2GB o...
     
High-performance and low-energy buffer mapping method for multiprocessor DSP systems
Found in: ACM Transactions on Embedded Computing Systems (TECS)
By Shuvra S. Bhattacharyya
Issue Date:March 2013
pp. 1-23
When implementing digital signal processing (DSP) applications onto multiprocessor systems, one significant problem in the viewpoints of performance is the memory wall. In this paper, to help alleviate the memory wall problem, we propose a novel, high-perf...
     
Teaching cross-platform design and testing methods for embedded systems using DICE
Found in: Proceedings of the 6th Workshop on Embedded Systems Education (WESE '11)
By Ayush Gupta, Chung-Ching Shen, Shuvra S. Bhattacharyya, William Plishker
Issue Date:October 2011
pp. 38-45
DICE (the DSPCAD Integrative Command Line Environment) is a package of utilities that facilitates efficient management of software projects. Key areas of emphasis in DICE are cross-platform operation, support for projects that integrate heterogeneous progr...
     
Multithreaded Simulation for Synchronous Dataflow Graphs
Found in: ACM Transactions on Design Automation of Electronic Systems (TODAES)
By Chia-Jui Hsu, Jose Luis Pino, Shuvra S. Bhattacharyya
Issue Date:June 2011
pp. 1-23
For system simulation, Synchronous DataFlow (SDF) has been widely used as a core model of computation in design tools for digital communication and signal processing systems. The traditional approach for simulating SDF graphs is to compute and execute stat...
     
Analysis of SystemC actor networks for efficient synthesis
Found in: ACM Transactions on Embedded Computing Systems (TECS)
By Christian Haubelt, Christian Zebelein, Joachim Falk, Joachim Keinert, Juergen Teich, Shuvra S. Bhattacharyya
Issue Date:December 2010
pp. 1-34
Applications in the signal processing domain are often modeled by dataflow graphs. Due to heterogeneous complexity requirements, these graphs contain both dynamic and static dataflow actors. In previous work, we presented a generalized clustering approach ...
     
Energy-driven distribution of signal processing applications across wireless sensor networks
Found in: ACM Transactions on Sensor Networks (TOSN)
By Chung-Ching Shen, Dong-Ik Ko, Neil Goldsman, Shuvra S. Bhattacharyya, William L. Plishker
Issue Date:June 2010
pp. 1-32
Wireless sensor network (WSN) applications have been studied extensively in recent years. Such applications involve resource-limited embedded sensor nodes that have small size and low power requirements. Based on the need for extended network lifetimes in ...
     
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