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Displaying 1-21 out of 21 total
Session Abstract
Found in: VLSI Test Symposium, IEEE
By Rubin A. Parekhji
Issue Date:May 2006
pp. 86-87
Large designs, larger test pattern volumes and longer test times have necessitated the use of test data and test time compression techniques built around the scan design paradigm. The adoption of these techniques is increasing. Much as well as they are und...
   
Panel Synopsis - How (In)Adequate is One Time Testing?
Found in: Test Conference, International
By Rubin A. Parekhji
Issue Date:October 2003
pp. 1279
No summary available.
   
Testing Embedded Cores and SOCs-DFT, ATPG and BIST Solutions
Found in: VLSI Design, International Conference on
By Rubin A. Parekhji
Issue Date:January 2003
pp. 17
This tutorial presents a range of design and test techniques and considerations for incorporating high level testability into high performance SOC designs, constructed using embedded cores. Different solutions are proposed around DFT, ATPG and BIST techniq...
   
Test Scheduling for Multicore SoCs with Dynamic Voltage Scaling and Multiple Voltage Islands
Found in: Asian Test Symposium
By Xrysovalantis Kavousianos,Krishnendu Chakrabarty,Arvind Jain,Rubin Parekhji
Issue Date:November 2011
pp. 33-39
In order to provide high performance with low power consumption, modern multicore chips employ dynamic voltage scaling and voltage islands that operate at multiple power-supply voltage settings. Effective defect screening for the embedded cores in such mul...
 
Multi-CoDec Configurations for Low Power and High Quality Scan Test
Found in: VLSI Design, International Conference on
By Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji, Srivaths Ravi
Issue Date:January 2011
pp. 370-375
Scan compression techniques are widely used to contain test application time and test data volume. Smart techniques exist to match the scan compression CoDec (compactor-decompressor) module with the DUT (design under test), to realize high levels of compre...
 
Robust detection of soft errors using delayed capture methodology
Found in: On-Line Testing Symposium, IEEE International
By V Prasanth, Virendra Singh, Rubin Parekhji
Issue Date:July 2010
pp. 277-282
With the scaling of technology node and voltage levels, the susceptibility of logic to soft errors is increasing. Hence it is very important to take care of soft errors in the combinational logic along with those in the sequential elements. In this paper, ...
 
Design techniques and tradeoffs in implementing non-destructive field test using logic BIST self-test
Found in: On-Line Testing Symposium, IEEE International
By Amit Dutta, Malav Shah, G. Swathi, Rubin A. Parekhji
Issue Date:June 2009
pp. 237-242
Periodic testing of electronic devices on the field during application execution is becoming increasingly important. In addition, some of these applications are embedded and real-time, requiring the system to be operational for extended periods. In such ap...
 
Evaluation of Entropy Driven Compression Bounds on Industrial Designs
Found in: Asian Test Symposium
By Srinivasulu Alampally, Jais Abraham, Rubin A. Parekhji, Rohit Kapur, T.W. Williams
Issue Date:November 2008
pp. 13-18
The use of scan based compression techniques is becoming mandatory on current designs. While high compression is desired to hold the test costs within limits, it is important to understand the bounds set by the entropy of the care bits required by differen...
 
Power Analysis and Reduction Techniques for Transition Fault Testing
Found in: Asian Test Symposium
By Khushboo Agarwal, Srinivas Vooka, Srivaths Ravi, Rubin Parekhji, Arjun Singh Gill
Issue Date:November 2008
pp. 403-408
This paper examines the differences in power consumption characteristics of two popular ATPG techniques for transition fault testing (TFT) -- launch off shift (LOS) and launch off capture (LOC). These differences have critical implications on the circuit s...
 
False Error Study of On-line Soft Error Detection Mechanisms
Found in: On-Line Testing Symposium, IEEE International
By M. Kiran Kumar Reddy, Bharadwaj S. Amrutur, Rubin A. Parekhji
Issue Date:July 2008
pp. 53-58
With technology scaling, vulnerability to soft errors in random logic is increasing. There is a need for on-line error detection and protection for logic gates even at sea level. The error checker is the key element for an on-line detection mechanism. We c...
 
A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips
Found in: VLSI Test Symposium, IEEE
By Rajesh Tiwari, Abhijeet Shrivastava, Mahit Warhadpande, Srivaths Ravi, Rubin Parekhji
Issue Date:May 2008
pp. 53-58
Conventional methods to assess the test data volume (TDV) of logic in system-on-chips (SoCs) use intuitive formulae that are often agnostic of the target automatic test equipment (ATE) hardware or the ATE test program compilation process. In this paper, we...
 
Modeling Techniques for Formal Verification of BIST Controllers and Their Integration into SOC Designs
Found in: VLSI Design, International Conference on
By Subir K. Roy, Rubin A. Parekhji
Issue Date:January 2007
pp. 364-372
This paper describes the methods and challenges for modeling BIST logic in complex SOCs to enable their verification using formal techniques. The main contributions of this paper are: (a) application of symbolic model checking to BIST logic verification, (...
 
Enhancements in Deterministic BIST Implementations for Improving Test of Complex SOCs
Found in: VLSI Design, International Conference on
By Sandeep Jain, Jais Abraham, Srinivas Kumar Vooka, Sumant Kale, Amit Dutta, Rubin Parekhji
Issue Date:January 2007
pp. 339-344
Innovative solutions have been proposed to reduce the test cost of SOC designs. STUMPS (Self-Test Using PRPG and MISR Structures) architecture based logic BIST (Built-In Self- Test) is one such popular solution which attempts to reduce the cost of scan bas...
 
Modified Stability Checking for On-line Error Detection
Found in: VLSI Design, International Conference on
By Satish Yada, Bharadwaj Amrutur, Rubin A. Parekhji
Issue Date:January 2007
pp. 787-792
We propose a unified error detection technique, based on stability checking, for on-line detection of delay, crosstalk and transient faults in combinational circuits and SEUs in sequential elements. Our method, called Modified Stability Checking (MSC), ove...
 
Choosing the Right Mix of At-speed Structural Test Patterns: Comparisons in Pattern Volume Reduction and Fault Detection Efficiency
Found in: Asian Test Symposium
By Sameer Goel, Rubin A. Parekhji
Issue Date:December 2005
pp. 330-336
The generation, qualification and validation of structural patterns for transition and path delay faults present several problems due to various design, tools and tester constraints. This paper proposes a flow for the generation and selection of a reduced ...
 
DFT for Low Cost SOC Test
Found in: Asian Test Symposium
By Rubin A. Parekhji
Issue Date:December 2005
pp. 451
Growing test costs impact the design and implementation of large and complex IP (intellectual property) modules, (often reused as embedded cores), as well as the construction of SOCs (systems-on-chip) using them. The modules must be designed for re-use in ...
   
DFT for Test Optimisations in a Complex Mixed-Signal SOC - Case Study on TI?s TNETD7300 ADSL Modem Device
Found in: Test Conference, International
By K. Nikila, Rubin A. Parekhji
Issue Date:October 2004
pp. 773-782
The design and integration challenges for SOCs include DFT for test integration to meet the test quality and test cost goals. This paper describes the DFT implementation on TNETD7300, a single chip ADSL modem SOC with analog and digital sub-systems, IP cor...
 
ITC 2003 panels: Part 1
Found in: IEEE Design and Test of Computers
By Carol Stolicny, Tapio Koivukangas, Rubin Parekhji, Ian G. Harris, Rob Aitken
Issue Date:March 2004
pp. 160-163
No summary available.
 
Built-in Self-test Technique for Selective Detection of Neighbourhood Pattern Sensitive Faults in Memories
Found in: VLSI Design, International Conference on
By Rajeshwar S. Sable, Ravindra P. Saraf, Rubin A. Parekhji, Arun N. Chandorkar
Issue Date:January 2004
pp. 753
Traditional tests for memories are based on conventional fault models, involving the address decoder, individual memory cells and a limited coupling between them. The algorithms used in these tests have been successively augmented to consider stronger coup...
 
Concurrent Error Detection Using Monitoring Machines
Found in: IEEE Design and Test of Computers
By Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar
Issue Date:September 1995
pp. 24-32
In circuits implementing system level functions, the correctness of the overall operation is critically dependent on the correctness of the control part. Therefore, concurrent error detection techniques for controllers implemented in integrated circuits ha...
 
A Framework to evaluate Test Tradeoffs in Embedded Core Based Systems-Case Study on TT's TMS320C27xx
Found in: Test Conference, International
By Jais Abraham, Narayan Prasad, Srinivasa Chakravarthy B.S, Ameet Bagwe, Rubin A. Parekhji
Issue Date:October 2000
pp. 417
Intellectual property cores are being widely used to enable rapid integration of entire systems onto chips. While allowing for rapid system prototyping and design, this methodology complicates the problem of testing them. Various design for test techniques...
 
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