Search For:

Displaying 1-15 out of 15 total
Guest Editors' Introduction: Micro's Top Picks from the Microarchitecture Conferences
Found in: IEEE Micro
By Ronny Ronen, Antonio González
Issue Date:January 2007
pp. 8-11
The guest editors introduce this special issue showcasing Micro's Top Picks from the Microarchitecture Conferences of 2006. They describe the issue's intensive submission and selection process. The articles focus on the design of resilient computing system...
 
Best of Both Latency and Throughput
Found in: Computer Design, International Conference on
By Ed Grochowski, Ronny Ronen, John Shen, Hong Wang
Issue Date:October 2004
pp. 236-243
This paper describes the tradeoff between latency performance and throughput performance in a power-constrained environment. We show that the key to achieving both excellent latency performance as well as excellent throughput performance is to dynamically ...
 
DDMR: Dynamic and Scalable Dual Modular Redundancy with Short Validation Intervals
Found in: IEEE Computer Architecture Letters
By Amit Golander, Shlomo Weiss, Ronny Ronen
Issue Date:July 2008
pp. 65-68
DMR (Dual Modular Redundancy) was suggested for increasing reliability. Classical DMR consists of pairs of cores that check each other and are pre-connected during manufacturing by dedicated links. In this paper we introduce the Dynamic Dual Modular Redund...
 
On Estimating Optimal Performance of CPU Dynamic Thermal Management
Found in: IEEE Computer Architecture Letters
By Aviad Cohen, Finkelstein Finkelstein, Avi Mendelson, Ronny Ronen, Dmitry Rudoy
Issue Date:January 2003
pp. N/A
In this paper we focus on dynamic thermal management(DTM) strategies that use dynamic voltage scaling (DVS)for power control. We perform a theoretical analysis targeted atestimating the optimal strategy, and show two facts: (1) whenthere is a gap between t...
 
Early Load Address Resolution via Register Tracking
Found in: Computer Architecture, International Symposium on
By Adi Yoaz, Maxim Kalaev, Ronny Ronen, Stephan Jourdan, Freddy Gabbay, Michael Bekerman
Issue Date:June 2000
pp. 306
Higher microprocessor frequencies accentuate the performance cost of memory accesses. This is especially noticeable in the Intel's IA32 architecture where lack of registers results in increased number of memory accesses. This paper presents novel, non-spec...
 
eXtended Block Cache
Found in: High-Performance Computer Architecture, International Symposium on
By Stephan Jourdan, Lihu Rappoport, Yoav Almog, Mattan Erez, Adi Yoaz, Ronny Ronen
Issue Date:January 2000
pp. 61
This paper describes a new instruction-supply mechanism, called the eXtended Block Cache (XBC). The goal of the XBC is to improve on the Trace Cache (TC) hit rate, while providing the same bandwidth. The improved hit rate is achieved by having the XBC a ne...
 
Speculation Techniques for Improving Load Related Instruction Scheduling
Found in: Computer Architecture, International Symposium on
By Adi Yoaz, Mattan Erez, Ronny Ronen, Stephan Jourdan
Issue Date:May 1999
pp. 0042
State of the art microprocessors achieve high performance by executing multiple instructions per cycle. In an out-of-order engine, the instruction scheduler is responsible for dispatching instructions to execution units based on dependencies, latencies, an...
 
Correlated Load-Address Predictors
Found in: Computer Architecture, International Symposium on
By Michael Bekerman, Stephan Jourdan, Ronny Ronen, Gilad Kirshenboim, Lihu Rappoport, Adi Yoaz, Uri Weiser
Issue Date:May 1999
pp. 0054
As microprocessors become faster, the relative performance cost of memory accesses increases. Bigger and faster caches significantly reduce the absolute load-to-use time delay. However, increase in processor operational frequencies impairs the relative loa...
 
Improving the energy efficiency of Big Cores
Found in: 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)
By Kenneth Czechowski,Victor W. Lee,Ed Grochowski,Ronny Ronen,Ronak Singhal,Richard Vuduc,Pradeep Dubey
Issue Date:June 2014
pp. 493-504
Traditionally, architectural innovations designed to boost single-threaded performance incur overhead costs which significantly increase power consumption. In many cases the increase in power exceeds the improvement in performance, resulting in a net incre...
   
Larrabee: a many-core Intel® architecture for visual computing
Found in: Proceedings of the 6th ACM conference on Computing frontiers (CF '09)
By Ronny Ronny Ronen
Issue Date:May 2009
pp. 225-225
The ample supply of transistors provided by advancements in process technology, combined with the increased difficultly to exploit single thread performance, moved the industry to populate several cores on a single die. This talk presents Larrabee -- the n...
     
Filtering Techniques to Improve Trace-Cache Efficiency
Found in: Parallel Architectures and Compilation Techniques, International Conference on
By Roni Rosner, Avi Mendelson, Ronny Ronen
Issue Date:September 2001
pp. 0037
Abstract: The trace cache is becoming an important building block of modern, wide-issue processors. So far, trace cache related research has been focused on increasing fetch bandwidth. Trace-caches have been shown too effectively increase the number of
 
Programming model for a heterogeneous x86 platform
Found in: Proceedings of the 2009 ACM SIGPLAN conference on Programming language design and implementation (PLDI '09)
By Avi Mendelson, Bratin Saha, Hu Chen, Jesse Fang, Mohan Rajagopalan, Peinan Zhang, Ronny Ronen, Shoumeng Yan, Xiaocheng Zhou, Ying Gao
Issue Date:June 2009
pp. 1-22
The client computing platform is moving towards a heterogeneous architecture consisting of a combination of cores focused on scalar performance, and a set of throughput-oriented cores. The throughput oriented cores (e.g. a GPU) may be connected over both c...
     
Selecting long atomic traces for high coverage
Found in: Proceedings of the 17th annual international conference on Supercomputing (ICS '03)
By Micha Moffie, Roni Rosner, Ronny Ronen, Yiannakis Sazeides
Issue Date:June 2003
pp. 2-11
This paper performs a comprehensive investigation of dynamic selection for long atomic traces. It introduces a classification of trace selection methods and discusses existing and novel dynamic selection approaches - including loop unrolling, procedure in-...
     
Micro-operation cache: a power aware frontend for the variable instruction length ISA
Found in: Proceedings of the 2001 international symposium on Low power electronics and design (ISLPED '01)
By Avi Mendelson, Baruch Solomon, Doron Orenstein, Ronny Ronen, Yoav Almog
Issue Date:August 2001
pp. 4-9
Wireless communications and more specifically, the fast growing penetration of cellular phones and cellular infrastructure are the major drivers for the development of new programmable Digital Signal Processors (DSPs). In this tutorial, an overview will be...
     
Early load address resolution via register tracking
Found in: Proceedings of the 27th annual international symposium on Computer architecture (ISCA '00)
By Adi Yoaz, Freddy Gabbay, Maxim Kalaev, Michael Bekerman, Ronny Ronen, Stephan Jourdan
Issue Date:June 2000
pp. 125-131
Higher microprocessor frequencies accentuate the performance cost of memory accesses. This is especially noticeable in the Intel's IA32 architecture where lack of registers results in increased number of memory accesses. This paper presents novel, non-spec...
     
 1