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Displaying 1-14 out of 14 total
Silicon Photonic Interconnects for Large-Scale Computer Systems
Found in: IEEE Micro
By Ron Ho,Philip Amberg,Eric Chang,Pranay Koka,Jon Lexau,Guoliang Li,Frankie Y. Liu,Herb Schwetman,Ivan Shubin,Hiren D. Thacker,Xuezhe Zheng,John E. Cunningham,Ashok V. Krishnamoorthy
Issue Date:January 2013
pp. 68-78
Optical interconnects play an integral role in large-scale digital computing, switching, and routing systems. The authors describe a path toward future many-chip modules based on silicon photonic interposers that stitch together tens of chips in a dense an...
 
Clocking Links in Multi-chip Packages: A Case Study
Found in: High-Performance Interconnects, Symposium on
By Tamer Ali, Dinesh Patil, Frankie Liu, Elad Alon, Jon Lexau, Chih-Kong Ken Yang, Ron Ho
Issue Date:August 2010
pp. 96-103
This brief note presents a case study for clocking links in multi-chip packages. A particular co-packaged multichip system design based on multi-Gbps silicon photonics global interconnect provides the context for our study of near-short range links, and we...
 
Optical Interconnects in the Data Center
Found in: High-Performance Interconnects, Symposium on
By Ron Ho, John E. Cunningham, Herb Schwetman, Xuezhe Zheng, Ashok V. Krishnamoorthy
Issue Date:August 2010
pp. 117-120
Optical interconnects in large-scale systems offer the possibility of new system topologies, with many multi-core processors and memories integrated together and densely co packaged. This opens up new possibilities in large-scale installations like data ce...
 
Optical Interconnect for High-End Computer Systems
Found in: IEEE Design and Test of Computers
By Ron Ho, Frankie Liu, Dinesh Patil, Xuezhe Zheng, Guoliang Li, Ivan Shubin, Elad Alon, Jon Lexau, Herb Schwetman, John E. Cunningham, Ashok V. Krishnamoorthy
Issue Date:July 2010
pp. 10-19
<p><it>Editor's note</it>:</p><p>Advances in silicon photonic technology have made possible the use of optical communication in large-scale chip arrays. This article shows how such a structure utilizes the high bandwidth of th...
 
Research Challenges for On-Chip Interconnection Networks
Found in: IEEE Micro
By John D. Owens, William J. Dally, Ron Ho, D.N. (Jay) Jayasimha, Stephen W. Keckler, Li-Shiuan Peh
Issue Date:September 2007
pp. 96-108
On-chip interconnection networks are rapidly becoming a key enabling technology for commodity multicore processors and SoCs common in consumer embedded systems. Last year, the National Science Foundation initiated a workshop that addressed upcoming researc...
 
Robust Energy-Efficient Adder Topologies
Found in: Computer Arithmetic, IEEE Symposium on
By Dinesh Patil, Omid Azizi, Mark Horowitz, Ron Ho, Rajesh Ananthraman
Issue Date:June 2007
pp. 16-28
In this paper we explore the relationship between adder topology and energy efficiency. We compare the energy-delay tradeoff curves of selected 32-bit adder topologies, to determine how architectural features and design techniques affect energy efficiency....
 
On-chip samplers for test and debug of asynchronous circuits
Found in: Asynchronous Circuits and Systems, International Symposium on
By Frankie Liu, Ron Ho, Robert Drost, Scott Fairbanks
Issue Date:March 2007
pp. 153-162
On-chip high-bandwidth sampling circuits supplement traditional test and debug techniques by non-invasively probing analog voltages for off-chip measurement. Existing circuits rely on sub-sampling techniques and thus require a synchronous clock. We extend ...
 
Challenges in Building a Flat-Bandwidth Memory Hierarchy for a Large-Scale Computer with Proximity Communication
Found in: High-Performance Interconnects, Symposium on
By Robert Drost, Craig Forrest, Bruce Guenin, Ron Ho, Ashok V. Krishnamoorthy, Danny Cohen, John E. Cunningham, Bernard Tourancheau, Arthur Zingher, Alex Chow, Gary Lauterbach, Ivan Sutherland
Issue Date:August 2005
pp. 13-22
Memory systems for conventional large-scale computers provide only limited bytes/s of data bandwidth when compared to their flop/s of instruction execution rate. The resulting bottleneck limits the bytes/flop that a processor may access from the full memor...
 
Smart Memories: A Modular Reconfigurable Architecture
Found in: Computer Architecture, International Symposium on
By Mark Horowitz, Nuwan Jayasena, Ron Ho, Tim Paaske, William J. Dally, Ken Mai
Issue Date:June 2000
pp. 161
Trends in VLSI technology scaling demand that future computing devices be narrowly focused to achieve high performance and high efficiency, yet also target the high volumes and low costs of widely applicable general purpose designs. To address these confli...
 
Interconnect Scaling Implications for CAD
Found in: Computer-Aided Design, International Conference on
By Ron Ho, Ken Mai, Hema Kapadia, Mark Horowitz
Issue Date:November 1999
pp. 425
Interconnect scaling to deep submicron processes presents many challenges to today's CAD flows. A recent analysis by Sylvester and Keutzer examined the behavior of average length wires under scaling, and controversially concluded that current CAD tools are...
 
A micro-architectural analysis of switched photonic multi-chip interconnects
Found in: Proceedings of the 39th Annual International Symposium on Computer Architecture (ISCA '12)
By Ashok V. Krishnamoorthy, Chia-Hsin Owen Chen, Herb Schwetman, Kannan Raj, Michael O. McCracken, Pranay Koka, Ron Ho, Xuezhe Zheng
Issue Date:June 2012
pp. 153-164
Silicon photonics is a promising technology to scale offchip bandwidth in a power-efficient manner. Given equivalent bandwidth, the flexibility of switched networks often leads to the assumption that they deliver greater performance than point-to-point net...
     
Silicon-photonic network architectures for scalable, power-efficient multi-chip systems
Found in: Proceedings of the 37th annual international symposium on Computer architecture (ISCA '10)
By Ashok V. Krishnamoorthy, Herb Schwetman, Michael O. McCracken, Pranay Koka, Ron Ho, Xuezhe Zheng
Issue Date:June 2010
pp. 72-ff
Scaling trends of logic, memories, and interconnect networks lead towards dense many-core chips. Unfortunately, process yields and reticle sizes limit the scalability of large single-chip systems. Multi-chip systems break free of these areal limits, but in...
     
High-performance ULSI: the real limiter to interconnect scaling
Found in: Proceedings of the 2005 international workshop on System level interconnect prediction (SLIP '05)
By Ron Ho
Issue Date:April 2005
pp. 3-3
In a classic paper at the 1995 IEEE Electron Devices Meeting, Mark Bohr outlined how interconnect scaling --- specifically, resistance scaling --- will ultimately limit the performance of future ULSI circuits [1]. Looking ahead, we see the reverse: constra...
     
Smart Memories: a modular reconfigurable architecture
Found in: Proceedings of the 27th annual international symposium on Computer architecture (ISCA '00)
By Ken Mai, Mark Horowitz, Nuwan Jayasena, Ron Ho, Tim Paaske, William J. Dally
Issue Date:June 2000
pp. 125-131
Trends in VLSI technology scaling demand that future computing devices be narrowly focused to achieve high performance and high efficiency, yet also target the high volumes and low costs of widely applicable general purpose designs. To address these confli...
     
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