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Displaying 1-6 out of 6 total
A Formalization of the Security Features of Physical Functions
Found in: Security and Privacy, IEEE Symposium on
By Frederik Armknecht, Roel Maes, Ahmad-Reza Sadeghi, Fran├žois-Xavier Standaert, Christian Wachsmann
Issue Date:May 2011
pp. 397-412
Physical attacks against cryptographic devices typically take advantage of information leakage (e.g., side-channels attacks) or erroneous computations (e.g., fault injection attacks). Preventing or detecting these attacks has become a challenging task in m...
Analysis and design of active IC metering schemes
Found in: Hardware-Oriented Security and Trust, IEEE International Workshop on
By Roel Maes, Dries Schellekens, Pim Tuyls, Ingrid Verbauwhede
Issue Date:July 2009
pp. 74-81
Outsourcing the fabrication of semiconductor devices to merchant foundries raises some issues concerning the IP protection of the design. Active hardware metering schemes try to counter piracy of integrated circuits by enforcing the fabrication plant to ru...
FPGA-based testing strategy for cryptographic chips: A case study on Elliptic Curve Processor for RFID tags
Found in: On-Line Testing Symposium, IEEE International
By Junfeng Fan, Miroslav Knezevic, Dusko Karaklajic, Roel Maes, Vladimir Rozic, Lejla Batina, Ingrid Verbauwhede
Issue Date:June 2009
pp. 189-191
Testing of cryptographic chips or components has one extra dimension: physical security. The chip designers should improve the design if it leaks too much information through side-channels, such as timing, power consumption, electric-magnetic radiation, an...
Extended abstract: The butterfly PUF protecting IP on every FPGA
Found in: Hardware-Oriented Security and Trust, IEEE International Workshop on
By Sandeep S. Kumar, Jorge Guajardo, Roel Maes, Geert-Jan Schrijen, Pim Tuyls
Issue Date:June 2008
pp. 67-70
IP protection of hardware designs is the most important requirement for many FPGA IP vendors. To this end, various solutions have been proposed by FPGA manufacturers based on the idea of bitstream encryption. An alternative solution was advocated in [18]. ...
Adapting voltage ramp-up time for temperature noise reduction on memory-based PUFs
Found in: 2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)
By Mafalda Cortez,Said Hamdioui,Vincent van der Leest,Roel Maes,Geert-Jan Schrijen
Issue Date:June 2013
pp. 35-40
The efficiency and cost of silicon PUF-based applications, and in particular key generators, are heavily impacted by the level of reproducibility of the bare PUF responses under varying operational circumstances. Error-correcting codes can be used to achie...
Physically unclonable functions: manufacturing variability as an unclonable device identifier
Found in: Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI (GLSVLSI '11)
By Ingrid Verbauwhede, Roel Maes
Issue Date:May 2011
pp. 455-460
CMOS process variations are considered a burden to IC developers since they introduce undesirable random variability between equally designed ICs. However, it was demonstrated that measuring this variability can also be profitable as a physically unclonabl...