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Displaying 1-16 out of 16 total
TRESCCA - Trustworthy Embedded Systems for Secure Cloud Computing
Found in: 2013 Eighth International Conference on Availability, Reliability and Security (ARES)
By Gunnar Schomaker,Andreas Herrholz,Guillaume Duc,Renaud Pacalet,Salvatore Raho,Miltos Grammatikakis,Marcello Coppola,Ignacio Garcia Vega
Issue Date:September 2013
pp. 844-845
Cloud Computing is an inevitable trend. In the near future almost every consumer electronic device will be connected to an ecosystem of third-party service partners, providing applications like payment systems, streamed content, etc using or producing sens...
 
DiplodocusDF, a Domain-Specific Modelling Language for Software Defined Radio Applications
Found in: 2012 38th EUROMICRO Conference on Software Engineering and Advanced Applications (SEAA)
By Jair Gonzalez-Pina,Rabea Ameur-Boulifa,Renaud Pacalet
Issue Date:September 2012
pp. 1-8
Given its intrinsic complexity, it is not efficient to develop software defined radio (SDR) systems following traditional methodologies. A new methodology is necessary, which should allow the description of the applications at higher abstraction levels. Th...
 
On-the-Fly Syndrome Check for LDPC Decoders
Found in: Wireless and Mobile Communications, International Conference on
By Erick Amador, Raymond Knopp, Renaud Pacalet, Vincent Rezard
Issue Date:September 2010
pp. 33-37
Modern VLSI decoders for low-density parity-check (LDPC) codes require high throughput performance while achieving high energy efficiency on the smallest possible footprint. In this paper we present a valuable optimization to the processing step known as s...
 
Hybrid Iteration Control on LDPC Decoders
Found in: Wireless and Mobile Communications, International Conference on
By Erick Amador, Raymond Knopp, Vincent Rezard, Renaud Pacalet
Issue Date:September 2010
pp. 102-106
Stopping criteria for the iterative decoding of low-density parity-check codes are considered. For a successful decoding task an inherent stopping criterion is used: the fulfillment of all parity-check constraints. For an unsuccessful task the decoder usua...
 
Dynamic Power Management on LDPC Decoders
Found in: VLSI, IEEE Computer Society Annual Symposium on
By Erick Amador, Raymond Knopp, Vincent Rezard, Renaud Pacalet
Issue Date:July 2010
pp. 416-421
This paper presents a dynamic power management strategy for the iterative decoding of low-density parity-check (LDPC) codes. We propose an online algorithm for adjusting the operation of a power manageable decoder. Decision making is based upon the monitor...
 
Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics
Found in: IEEE Transactions on Computers
By Sylvain Guilley, Laurent Sauvage, Florent Flament, Vinh-Nga Vong, Philippe Hoogvorst, Renaud Pacalet
Issue Date:September 2010
pp. 1250-1263
Cryptographic circuits are nowadays subject to attacks that no longer focus on the algorithm but rather on its physical implementation. Attacks exploiting information leaked by the hardware implementation are called side-channel attacks (SCAs). Among these...
 
Flexible Baseband Architectures for Future Wireless Systems
Found in: Digital Systems Design, Euromicro Symposium on
By Najam-ul-Islam Muhammad, Rizwan Rasheed, Renaud Pacalet, Raymond Knopp, Karim Khalfallah
Issue Date:September 2008
pp. 39-46
The mobile communication systems today, have different radio spectrum, radio access technologies, and protocol stacks depending on the network being utilized. This gives rise to need of a flexible hardware platform that is capable of supporting all the dif...
 
Silicon-level Solutions to Counteract Passive and Active Attacks
Found in: Fault Diagnosis and Tolerance in Cryptography, Workshop on
By Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane, Renaud Pacalet
Issue Date:August 2008
pp. 3-17
This article presents a family of cryptographic ASICs, called SecMat, designed in CMOS 130 nanometer technology by the authors with the help of STMicroelectronics.The purpose of these prototype circuits is to experience with the published ``implementation-...
 
Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks
Found in: IEEE Transactions on Computers
By Sylvain Guilley, Laurent Sauvage, Philippe Hoogvorst, Renaud Pacalet, Guido Marco Bertoni, Sumanta Chaudhuri
Issue Date:November 2008
pp. 1482-1497
Power-constant logic styles are promising solutions to counter-act side-channel attacks on sensitive cryptographic devices. Recently, one vulnerability has been identified in a standard-cell based power-constant logic called WDDL. Another logic, nicknamed ...
 
Application Specific Processors for Multimedia Applications
Found in: Computational Science and Engineering, IEEE International Conference on
By Muhammad Rashid, Ludovic Apvrille, Renaud Pacalet
Issue Date:July 2008
pp. 109-116
A well-known challenge during processor design is to obtain best possible results for a typical target application domain by combining flexibility and computational performance. ASIPs (Application Specific Instruction Set Processors) provide a tradeoff bet...
 
Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors
Found in: IEEE Design and Test of Computers
By Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Renaud Pacalet, Yves Mathieu
Issue Date:November 2007
pp. 546-555
This article presents a comprehensive back-end design flow that enables the realization of constant-power cryptoprocessors, natively protected against side-channel attacks exploiting the instant power consumption. The proposed methodology is based on a ful...
 
Abstract Application Modeling for System Design Space Exploration
Found in: Digital Systems Design, Euromicro Symposium on
By Muhammad Waseem, Ludovic Apvrille, Rabea Ameur-Boulifa, Sophie Coudert, Renaud Pacalet
Issue Date:September 2006
pp. 331-337
The increasing complexity of System-on-Chip (SoC) requires a complete reexamination of design and validation methods prior to final implementation whereas faster system design space exploration is today?s requirement to speed up the design process in order...
 
CMOS Structures Suitable for Secured Hardware
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet, Jean Provost
Issue Date:February 2004
pp. 21414
Unsecured electronic circuits leak physical syndromes correlated to the data they handle. Side-channels attacks, like SPA or DPA, exploit this information leakage. We provide balanced and memoryless CMOS structures for a 2-input secured NAND gate.
   
SecBus, a Software/Hardware Architecture for Securing External Memories
Found in: 2014 2nd IEEE International Conference on Mobile Cloud Computing, Services, and Engineering (MobileCloud)
By Jeremie Brunel,Renaud Pacalet,Salaheddine Ouaarab,Guillaume Duc
Issue Date:April 2014
pp. 277-282
Embedded systems are ubiquitous nowadays. In many cases, they manipulate sensitive applications or data and may be the target of logical or physical attacks. On systems that contain a System-on-Chip connected to an external memory, which is the case of num...
 
High-Level System Modeling for Rapid HW/SW Architecture Exploration
Found in: Rapid System Prototyping, IEEE International Workshop on
By Chafic Jaber, Andreas Kanstein, Ludovic Apvrille, Amer Baghdadi, Patricia Le Moënner, Renaud Pacalet
Issue Date:June 2009
pp. 88-94
The increasing complexity of system-on-chip design – especially the software part of those systems – has stimulated much research work on design space exploration at the early stages of system development. In this paper we propose a new methodology for sys...
 
Optimum LDPC decoder: a memory architecture problem
Found in: Proceedings of the 46th Annual Design Automation Conference (DAC '09)
By Erick Amador, Renaud Pacalet, Vincent Rezard
Issue Date:July 2009
pp. 891-896
This paper addresses a frequently overlooked problem: designing a memory architecture for an LDPC decoder. We analyze the requirements to support the codes defined in the IEEE 802.11n and 802.16e standards. We show a design methodology for a flexible memor...
     
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