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Displaying 1-32 out of 32 total
Guest Editors' Introduction - Special Issue on Network-on-Chip
Found in: IEEE Transactions on Computers
By Ran Ginosar,Karam S. Chatha
Issue Date:March 2014
pp. 527-528
Network-on-Chip (NoC) has emerged as a key architecture component that determines the overall performance, power, and area (PPA) of a contemporary System-on-Chip (SoC) device. The PPA characteristics of NoC are influenced by a wide range of issues, includi...
 
Metastability and Synchronizers: A Tutorial
Found in: IEEE Design and Test of Computers
By Ran Ginosar
Issue Date:September 2011
pp. 23-35
Editors' note:Metastability can arise whenever a signal is sampled close to a transition, leading to indecision as to its correct value. Synchronizer circuits, which guard against metastability, are becoming ubiquitous with the proliferation of timing doma...
 
Performance of a Hardware Scheduler for Many-core Architecture
Found in: 2012 IEEE 14th Int'l Conf. on High Performance Computing and Communication (HPCC) & 2012 IEEE 9th Int'l Conf. on Embedded Software and Systems (ICESS)
By Itai Avron,Ran Ginosar
Issue Date:June 2012
pp. 151-160
A hardware scheduler for many-core architectures enables fast scheduling and allocation of fine granularity tasks to all cores. We present performance evaluation of a hardware scheduler for HyperCore, a many-core architecture. The evaluation is based on an...
 
The Devolution of Synchronizers
Found in: Asynchronous Circuits and Systems, International Symposium on
By Salomon Beer, Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin, Avinoam Kolodny
Issue Date:May 2010
pp. 94-103
Synchronizers play a key role in multi-clock domain systems on chip. Traditionally, improvement of synchronization parameters with scaling has been assumed. In particular, the resolution time constant (tau) has been expected to scale proportionally to the ...
 
Access Regulation to Hot-Modules in Wormhole NoCs
Found in: Networks-on-Chip, International Symposium on
By Isask'har Walter, Israel Cidon, Ran Ginosar, Avinoam Kolodny
Issue Date:May 2007
pp. 137-148
Network on Chip (NoC) may be the primary interconnect mechanism for future Systems-on-Chip (SoC). Real-life SoCs typically include hot-modules such as DRAM controller or floating point unit, which are bandwidth limited and in high demand by other units. In...
 
QNoC Asynchronous Router with Dynamic Virtual Channel Allocation
Found in: Networks-on-Chip, International Symposium on
By Rostislav (Reuven) Dobkin, Ran Ginosar, Israel Cidon
Issue Date:May 2007
pp. 218
An asynchronous router for Quality-of service NoC is presented. It combines multiple service levels (SL) with multiple equal-priority virtual channels (VC) within each level. The VCs are assigned dynamically per each link. A different number of VCs may be ...
   
An Asynchronous Router for Multiple Service Levels Networks on Chip
Found in: Asynchronous Circuits and Systems, International Symposium on
By Dobkin (Reuven) Rostislav, Victoria Vishnyakov, Eyal Friedman, Ran Ginosar
Issue Date:March 2005
pp. 44-53
Networks on Chip that can guarantee Quality of Service (QNoC) are based on special routers that can support multiple service levels. GALS SoCs call for asynchronous NoC implementations, to eliminate the need for synchronization when crossing clock domains....
 
Timing Measurements of Synchronization Circuits
Found in: Asynchronous Circuits and Systems, International Symposium on
By Yaron Semiat, Ran Ginosar
Issue Date:May 2003
pp. 68
A regular (two-flop) synchronizer and six multi-synchronous synchronizers are implemented on a programmable logic device and are measured. An experiment system and method for measuring synchronizers and metastable flip-flops are described. Two separate set...
 
Fourteen Ways to Fool Your Synchronizer
Found in: Asynchronous Circuits and Systems, International Symposium on
By Ran Ginosar
Issue Date:May 2003
pp. 89
Transferring data between mutually asynchronous clock domains requires safe synchronization. However, the exact nature of synchronization sometimes eludes designers, and as a result synchronization circuits get
 
MTBF Estimation in Coherent Clock Domains
Found in: 2013 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)
By Salomon Beer,Ran Ginosar,Rostislav Dobkin,Yoav Weizman
Issue Date:May 2013
pp. 166-173
Special synchronizers exist for special clock relations such as mesochronous, multi-synchronous and ratiochronous clocks, while variants of N-flip-flop synchronizers are employed when the communicating clocks are asynchronous. N-flip-flop synchronizers are...
 
Network-on-Chip Architectures for Neural Networks
Found in: Networks-on-Chip, International Symposium on
By Dmitri Vainbrand, Ran Ginosar
Issue Date:May 2010
pp. 135-144
Providing highly flexible connectivity is a major architectural challenge for hardware implementation of reconfigurable neural networks. We perform an analytical evaluation and comparison of different configurable interconnect architectures (mesh NoC, tree...
 
The Power of Priority: NoC Based Distributed Cache Coherency
Found in: Networks-on-Chip, International Symposium on
By Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, Avinoam Kolodny
Issue Date:May 2007
pp. 117-126
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Multi Processors (CMPs). We address previously proposed CMP architectures based ...
 
High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link
Found in: Asynchronous Circuits and Systems, International Symposium on
By Rostislav Reuven Dobkin, Yevgeny Perelman, Tuvia Liran, Ran Ginosar, Avinoam Kolodny
Issue Date:March 2007
pp. 3-14
A high data rate asynchronous bit-serial link for long-range on-chip communication is presented. The data bit cycle time is equal to a single gate delay, enabling 67Gbps throughput in 65nm technology. The serial link incurs lower power and area costs relat...
 
Fast Asynchronous Shift Register for Bit-Serial Communication
Found in: Asynchronous Circuits and Systems, International Symposium on
By Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny
Issue Date:March 2006
pp. 117-127
A fast asynchronous shift register is used as the serializer and de-serializer in a novel bit-serial on-chip communication link. The link employs two-phase transition-based LEDR encoding. Acknowledgement is generated only at the word level, rather than bit...
 
Asynchronous Design By Conversion: Converting Synchronous Circuits into Asynchronous Ones
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Alex Branover, Rakefet Kol, Ran Ginosar
Issue Date:February 2004
pp. 20870
A novel methodology and algorithm for the design of large low-power asynchronous systems are described. The system is synthesized by a commercial tool as a synchronous circuit, and subsequently converted into an asynchronous one. The conversion algorithm c...
 
CAD Directions for High Performance Asynchronous Circuits
Found in: Design Automation Conference
By Ken Stevens, Shai Rotem, Steven M. Burns, Jordi Cortadella, Ran Ginosar, Michael Kishinevsky, Marly Roncken
Issue Date:June 1999
pp. 116-121
This paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using Relative Timing. This methodology was developed for a prototype iA32 instruction length decoding and stee...
 
Relative Timing
Found in: Asynchronous Circuits and Systems, International Symposium on
By Ken Stevens, Shai Rotem, Ran Ginosar
Issue Date:April 1999
pp. 208
Relative Timing is introduced as an informal method for aggressive asynchronous design. It is demonstrated on three example circuits (C-Element, FIFO, and RAPPID Tag Unit), facilitating transformations from speed-independent circuits to burst-mode, relativ...
 
RAPPID: An Asynchronous Instruction Length Decoder
Found in: Asynchronous Circuits and Systems, International Symposium on
By Shai Rotem, Ken Stevens, Charles Dike, Marly Roncken, Boris Agapiev, Ran Ginosar, Rakefet Kol, Peter Beerel, Chris Myers, Kenneth Yun
Issue Date:April 1999
pp. 60
This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture. RAPPID (
 
Metastability in Better-Than-Worst-Case Designs
Found in: 2014 20th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)
By Salomon Beer,Marco Cannizzaro,Jordi Cortadella,Ran Ginosar,Luciano Lavagno
Issue Date:May 2014
pp. 101-102
Better-Than-Worst-Case-Designs use timing speculation to run with a cycle period faster than the one required for worst-case conditions. This speculation may produce timing violations and metastability that result in failures and non-deterministic timing b...
 
Generalized MultiAmdahl: Optimization of Heterogeneous Multi-Accelerator SoC
Found in: IEEE Computer Architecture Letters
By Amir Morad,Tomer Y. Morad,Yavits Leonid,Ran Ginosar,Uri Weiser
Issue Date:January 2014
pp. 1-1
Consider a workload comprising a consecutive sequence of program execution segments, where each segment can either be executed on general purpose processor or offloaded to a hardware accelerator. An analytical optimization framework based on MultiAmdhal fr...
 
Energy Aware Race to Halt: A Down to EARtH Approach for Platform Energy Management
Found in: IEEE Computer Architecture Letters
By Rotem Efraim,Ran Ginosar,C. Weiser,Avi Mendelson
Issue Date:January 2014
pp. 1-1
The EARtH algorithm finds the optimal voltage and frequency operational point of the processor in order to achieve minimum energy of the computing platform. The algorithm is based on a theoretical model employing a small number of parameters, which are ext...
 
Computer Architecture With Associative Processor Replacing Last Level Cache and SIMD Accelerator
Found in: IEEE Transactions on Computers
By Leonid Yavits,Amir Morad,Ran Ginosar
Issue Date:November 2013
pp. 1
This study presents a computer architecture where a last level cache and a SIMD accelerator are replaced by an Associative Processor. Associative Processor combines data storage and data processing, and functions as a massively parallel SIMD processor and ...
 
Cache Hierarchy Optimization
Found in: IEEE Computer Architecture Letters
By Leonid Yavits,Amir Morad,Ran Ginosar
Issue Date:July 2013
pp. 1
Abstract— Power consumption, off-chip memory bandwidth, chip area and Network on Chip (NoC) capacity are among main chip resources limiting the scalability of Chip Multiprocessors (CMP). A closed form analytical solution for optimizing the CM...
 
Adaptive Synchronization
Found in: Computer Design, International Conference on
By Ran Ginosar, Rakefet Kol
Issue Date:October 1998
pp. 188
Delay variations are typically accounted for by increasing cycle time margins. Adaptive Synchronization eliminates this on inter-modular interfaces in very large, high performance chips. The chip is divided into multiple smaller synchronous modules. Multi-...
 
Multiple clock and voltage domains for chip multi processors
Found in: Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (Micro-42)
By Avi Mendelson, Efraim Rotem, Ran Ginosar, Uri Weiser
Issue Date:December 2009
pp. 459-468
Power and thermal are major constraints for delivering compute performance in high-end CPU and are expected to be so in the future. CMP is becoming important by delivering more compute performance within the power constraints. Dynamic Voltage and Frequency...
     
Power efficient tree-based crosslinks for skew reduction
Found in: Proceedings of the 19th ACM Great Lakes symposium on VLSI (GLSVLSI '09)
By Avinoam Kolodny, Eby G. Friedman, Inna Vaisband, Ran Ginosar
Issue Date:May 2009
pp. 375-376
Clock distribution networks are an important design issue that is highly dependent on delay variations and load imbalances, while requiring power efficiency. Existing mesh solutions significantly increase the dissipated power, whereas existing link based m...
     
Parallel vs. serial on-chip communication
Found in: Proceedings of the 2008 international workshop on System level interconnect prediction (SLIP '08)
By Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar, Rostislav Reuven Dobkin
Issue Date:April 2008
pp. 24-31
Synchronous parallel links are widely used in modern VLSI designs for on-chip inter-module communication. Long range parallel links occupy large area and incur high capacitive load, high leakage power and cross-coupling noise. The problems exacerbate for a...
     
Timing optimization in logic with interconnect
Found in: Proceedings of the 2008 international workshop on System level interconnect prediction (SLIP '08)
By Arkadiy Morgenshtein, Avinoam Kolodny, Eby G. Friedman, Ran Ginosar
Issue Date:April 2008
pp. 24-31
Timing optimization in logic paths with wires has become an important issue in the VLSI circuit design process. Existing techniques for minimizing delay treat only the relatively rare cases of logic without wires (logical effort) or logic with a long resis...
     
Routing table minimization for irregular mesh NoCs
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '07)
By Avinoam Kolodny, Evgeny Bolotin, Israel Cidon, Ran Ginosar
Issue Date:April 2007
pp. 942-947
The majority of current Network on Chip (NoC) architectures employ mesh topology and use simple static routing, to reduce power and area. However, regular mesh topology is unrealistic due to variations in module sizes and shapes, and is not suitable for ap...
     
CAD directions for high performance asynchronous circuits
Found in: Proceedings of the 36th ACM/IEEE conference on Design automation conference (DAC '99)
By Jordi Cortadella, Ken Stevens, Marly Roncken, Michael Kishinevsky, Ran Ginosar, Shai Rotem, Steven M. Burns
Issue Date:June 1999
pp. 116-121
We present the SpecSyn system-level design environment supp orting the sp ecify-explor e-refine (SER) designparadigm. This thr ee-step appr oach includes precise specification of system functionality, rapid explor ation of numerous system-level design opti...
     
A low power video processor
Found in: Proceedings of the 1998 international symposium on Low power electronics and design (ISLPED '98)
By Ran Ginosar, Uzi Zangi
Issue Date:August 1998
pp. 136-138
Multiple power saving methods were applied to a video processor for color digital video and still cameras. Architectural level methods failed to save power: asynchronous design, dynamic voltage scaling, bus switching minimization, pipeline stage merging, r...
     
Kin: a high performance asynchronous processor architecture
Found in: Proceedings of the 12th international conference on Supercomputing (ICS '98)
By Rakefet Kol, Ran Ginosar
Issue Date:July 1998
pp. 433-440
To minimize the amount of computation and storage for parallel sparse factorization, sparse matrices have to be reordered prior to factorization. We show that none of the popular ordering heuristics proposed before, namely, mulitple minimum degree and nest...
     
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