Search For:

Displaying 1-17 out of 17 total
Net by Net Routing with a New Path Search Algorithm
Found in: Integrated Circuit Design and System Design, Symposium on
By M. Johann, R. Reis
Issue Date:September 2000
pp. 144
Net by net routing is still a very important technique used to make connections in VLSI circuits. The maze routing algorithms used for this purpose correspond to shortest path searches derived from basic BFS or from A*, with many dedicated improvements. Th...
 
Injecting Multiple Upsets in a SEU Tolerant 8051 Micro-Controller
Found in: On-Line Testing Workshop, IEEE International
By F. Lima, L. Carro, R. Velazco, R. Reis
Issue Date:July 2002
pp. 194
This paper investigates the behavior of a SEU tolerant 8051-like micro-controller protected by single error correction Hamming Code in the presence of multiple upsets. Upsets were randomly injected in all sensitive parts of the design. The experiment was e...
   
Analyzing Area and Performance Penalty of Protecting Different Digital Modules with Hamming Code and Triple Modular Redundancy
Found in: Integrated Circuit Design and System Design, Symposium on
By R. Hentschke, F. Marques, F. Lima, L. Carro, A. Susin, R. Reis
Issue Date:September 2002
pp. 95
This work compares two fault tolerance techniques, Hamming code and Triple Modular Redundancy (TMR), that are largely used to mitigate Single Event Upsets in integrated circuits, in terms of area and performance penalty. Both techniques were implemented in...
 
Built-in aging monitoring for safety-critical applications
Found in: On-Line Testing Symposium, IEEE International
By J.C. Vazquez, V. Champac, A.M. Ziesemer, R. Reis, I.C. Teixeira, M.B. Santos, J.P. Teixeira
Issue Date:June 2009
pp. 9-14
Complex electronic systems for safety or mission-critical applications (automotive, space) must operate for many years in harsh environments. Reliability issues are worsening with device scaling down, while performance and quality requirements are increasi...
 
Designing a Radiation Hardened 8051-Like Micro-Controller
Found in: Integrated Circuit Design and System Design, Symposium on
By F.G. de Lima, E. Cota, L. Carro, M. Lubaszewski, R. Reis, R. Velazco, S. Rezgui
Issue Date:September 2000
pp. 255
This paper presents a prototype of a hardened version of the 8051 micro-controller, able to assure reliable operation in the presence of bit flips caused by radiation. Aiming at avoiding such faults in the 8051 micro-controller, Hamming code protection was...
 
ATG-Based Timing Analysis of Circuits Containing Complex Gates
Found in: Integrated Circuit Design and System Design, Symposium on
By J.L. Guntzel, A.C. Medina Pinto, E. d'Avila, R. Reis
Issue Date:September 2000
pp. 21
Most of the false path-aware timing analysis algorithms were originally developed for circuits made of simple gates, i.e. ANDs/NANDs, ORs/NORs and inverters. However, the availability of efficient CMOS macrocell generators and
 
Topological Parameters for Library Free Technology Mapping
Found in: Integrated Circuit Design and System Design, Symposium on
By A. Reis, R. Reis, M. Robert
Issue Date:February 1998
pp. 213
No summary available.
 
SisECO: Design of an Echo-Canceling IC for Base Band Modems
Found in: Integrated Circuit Design and System Design, Symposium on
By L. Agostini, G. Stemmer, A. Prado, R. Pacheco, T. Campos, S. Bampi, R. Reis
Issue Date:September 2000
pp. 216
This paper presents the design of SisECO, an echo-cancelling integrated circuit for ISDN modems operating in base band. The FIR adaptative filtering is the main function of the chip. The adaptation algorithm used is the LMS (Least Mean Square) type. The pa...
 
Improving Logic Density of QCL Masterslices by using Universal Logic Gates
Found in: Integrated Circuit Design and System Design, Symposium on
By J. G√ľntzel, M. Johann, L. Carro, F. Gusmao de Lima, R. Reis
Issue Date:February 1998
pp. 204
No summary available.
 
LASCA-Interconnect Parasitic Extraction Tool for Deep-Submicron IC Design
Found in: Integrated Circuit Design and System Design, Symposium on
By F.K. Ferreira, F. Moraes, R. Reis
Issue Date:September 2000
pp. 327
A fast capacitance and resistance extraction tool (wire extractor) is presented. Five models are implemented: ground capacitances, ground plus coupling capacitances and RC models (L, /spl pi/ and T lumped). The designer can choose one of these models accor...
 
Predictive error detection by on-line aging monitoring
Found in: On-Line Testing Symposium, IEEE International
By J. C. Vazquez, V. Champac, A. M. Ziesemer, R. Reis, J. Semiao, I. C. Teixeira, M. B. Santos, J. P. Teixeira
Issue Date:July 2010
pp. 9-14
The purpose of this paper is to present a predictive error detection methodology, based on monitoring of long-term performance degradation of semiconductor systems. Delay variation is used to sense timing degradation due to aging (namely, due to NBTI), or ...
 
Comparing transient-fault effects on synchronous and on asynchronous circuits
Found in: On-Line Testing Symposium, IEEE International
By R. Possamai Bastos, Y. Monnet, G. Sicard, F. Kastensmidt, M. Renaudin, R. Reis
Issue Date:June 2009
pp. 29-34
A methodology to evaluate transient-fault effects on synchronous and asynchronous is presented in this work. It is developed by means of fault-injection simulation campaigns on gate-level circuit implementations. The methodology is able to deal with the pa...
 
WTROPIC: A WWW-Based Macro-Cell Generator
Found in: Integrated Circuit Design and System Design, Symposium on
By J.L. Fragoso, F. Moraes, R. Reis
Issue Date:September 2000
pp. 133
This paper presents a www-based macro-cell generator tool integrated in a www-based framework. The Wtropic tool allows user connections through the Internet and it provides a communication layer to execute the physical synthesis tool remotely from any mach...
 
Microelectronics Education using WWW and CAD Tools
Found in: Integrated Circuit Design and System Design, Symposium on
By R. Reis, L. Indrusiak
Issue Date:February 1998
pp. 31
No summary available.
 
Functional verification of logic modules for a Gigabit Ethernet switch
Found in: Latin American Test Workshop
By J. Tonfat,G. Neuberger,R. Reis
Issue Date:March 2011
pp. 1-4
This work presents the functional verification of logic modules for a Gigabit Ethernet (GigE) Switch for an ASIC based on the NetFPGA platform. A coverage-driven constrained random stimulus approach is used. It is implemented in a layered-testbench environ...
 
Comparative Analysis and Application of Data Repository Infrastructure for Collaboration-Enabled Distributed Design Environments
Found in: Design, Automation and Test in Europe Conference and Exhibition
By L. Indrusiak, M. Glesner, R. Reis
Issue Date:March 2002
pp. 1130
No summary available.
   
A Case Study for a WWW based CAD Framework
Found in: Integrated Circuit Design and System Design, Symposium on
By L. Indrusiak, R. Reis
Issue Date:February 1998
pp. 116
No summary available.
 
 1