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A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM
Found in: Low Power Electronics and Design, International Symposium on
By Ki Chul Chun, Pulkit Jain, Chris H. Kim
Issue Date:August 2009
pp. 119-120
A logic-compatible low power eDRAM is demonstrated in 65nm CMOS achieving a retention time of 1.25msec and a static power dissipation of 91.3µW/Mb at 0.9V, 85ºC. A boosted 3T gain cell enhances data retention time and read speed. A regulated bit-line write...
 
Enhancing beneficial jitter using phase-shifted clock distribution
Found in: Low Power Electronics and Design, International Symposium on
By Dong Jiao, Jie Gu, Pulkit Jain, Chris Kim
Issue Date:August 2008
pp. 21-26
Clock jitter is generally considered undesirable but recent publications have shown that it can actually improve the timing margin. This paper investigates the
 
A multi-story power delivery technique for 3D integrated circuits
Found in: Low Power Electronics and Design, International Symposium on
By Pulkit Jain, Tae-Hyoung Kim, John Keane, Chris H. Kim
Issue Date:August 2008
pp. 57-62
Integrating circuits in the vertical direction can alleviate interconnect related problems and enable heterogeneous chips to be stacked in a single package with a small form factor. This paper addresses the power delivery issues in 3D chips revealing some ...
 
Silicon Odometers: Compact In-situ Aging Sensors for Robust System Design
Found in: IEEE Micro
By Xiaofei Wang,John Keane,Tony Tae-Hyoung Kim,Pulkit Jain,Qianying Tang,Chris H. Kim
Issue Date:February 2014
pp. 1
Circuit reliability issues such as Bias Temperature Instability (BTI), Hot Carrier Injection (HCI), Time Dependent Dielectric Breakdown (TDDB) Electromigration (EM), and Random Telegraph Noise (RTN) have become a growing concern with technology scaling. Pr...
 
A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM
Found in: Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design (ISLPED '09)
By Chris H. Kim, Ki Chul Chun, Pulkit Jain
Issue Date:August 2009
pp. 1-2
A logic-compatible low power eDRAM is demonstrated in 65nm CMOS achieving a retention time of 1.25msec and a static power dissipation of 91.3µW/Mb at 0.9V, 85ºC. A boosted 3T gain cell enhances data retention time and read speed. A regulated bit-...
     
A multi-story power delivery technique for 3D integrated circuits
Found in: Proceeding of the thirteenth international symposium on Low power electronics and design (ISLPED '08)
By Chris H. Kim, John Keane, Pulkit Jain, Tae-Hyoung Kim
Issue Date:August 2008
pp. 383-384
Integrating circuits in the vertical direction can alleviate interconnect related problems and enable heterogeneous chips to be stacked in a single package with a small form factor. This paper addresses the power delivery issues in 3D chips revealing some ...
     
Enhancing beneficial jitter using phase-shifted clock distribution
Found in: Proceeding of the thirteenth international symposium on Low power electronics and design (ISLPED '08)
By Chris Kim, Dong Jiao, Jie Gu, Pulkit Jain
Issue Date:August 2008
pp. 383-384
Clock jitter is generally considered undesirable but recent publications have shown that it can actually improve the timing margin. This paper investigates the "beneficial jitter" effect and presents an accurate analytical model which is verified with HSPI...
     
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