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Displaying 1-50 out of 82 total
Low-Power Design and Temperature Management
Found in: IEEE Micro
By Kevin Skadron, Pradip Bose, Kanad Ghose, Resit Sendag, Joshua J. Yi, Derek Chiou
Issue Date:November 2007
pp. 46-57
One of the primary concerns for microprocessor designers has always been balancing power and thermal management while minimizing performance loss. Rather than generate solutions to this dilemma, the advent of multicore chips has raised a host of new challe...
 
Keynote II: Integrated modeling challenges in extreme-scale computing
Found in: Performance Analysis of Systems and Software, IEEE International Symmposium on
By Pradip Bose
Issue Date:April 2011
pp. 133
Extreme-scale computer systems of the future target orders of magnitude improvement in performance over current large-scale server or supercomputing systems. These targets must be achieved for the same power consumption and reliability at the system level....
   
Guest Editors' Introduction: Reliability Challenges in Nano-CMOS Design
Found in: IEEE Design and Test of Computers
By Yu Cao, Jim Tschanz, Pradip Bose
Issue Date:September 2009
pp. 6-7
<p><scp>VLSI</scp> design is driven by an ever-increasing challenge to cope with unreliable components at the device, circuit, and system levels. Reliability challenges include, for example, bias-temperature instability (BTI), dielectric ...
 
Guest Editors' Introduction: Energy-Efficient Design
Found in: IEEE Micro
By Kunio Uchiyama, Pradip Bose
Issue Date:September 2005
pp. 6-9
Energy efficiency has been a key design constraint for microprocessor development teams since the late 1990s. The fundamental technological issues that have led to this point are quite well understood at this time by industry and academia. Although active ...
 
High performance at affordable power
Found in: IEEE Micro
By Pradip Bose
Issue Date:September 2005
pp. 5
Regardless of what chip a team is designing, energy efficiency is probably one of the most important criteria. Achieving high performance at affordable power (and therefore, cost) is the overall system goal across a whole range of products that serve the h...
 
Power-Aware, Reliable Microprocessor Design
Found in: VLSI Design, International Conference on
By Pradip Bose
Issue Date:January 2005
pp. 3
No summary available.
   
Guest Editors' Introduction: Micro's Top Picks from Microarchitecture Conferences
Found in: IEEE Micro
By Charles Moore, Kevin W. Rudd, Ruby B. Lee, Pradip Bose
Issue Date:November 2003
pp. 8-10
<p></p>
 
Guest Editors' Introduction: Power and Complexity Aware Design
Found in: IEEE Micro
By Pradip Bose, David H. Albonesi, Diana Marculescu
Issue Date:September 2003
pp. 8-11
No summary available.
 
SMT Switch: Software Mechanisms for Power Shifting
Found in: IEEE Computer Architecture Letters
By Priyanka Tembey,Augusto Vega,Alper Buyuktosunoglu,Dilma Da Silva,Pradip Bose
Issue Date:July 2013
pp. 67-70
Simultaneous multithreading (SMT) as a processor design to achieve higher levels of system and application throughput is a well-accepted and deployed technique in most desktop and server processors. We study the power implications of varying SMT levels i.e...
 
Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks
Found in: 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
By Ramon Bertran,Alper Buyuktosunoglu,Meeta S. Gupta,Marc Gonzalez,Pradip Bose
Issue Date:December 2012
pp. 199-211
Microprocessor-based systems today are composed of multi-core, multi-threaded processors with complex cache hierarchies and gigabytes of main memory. Accurate characterization of such a system, through predictive pre-silicon modeling and/or diagnostic post...
 
Architectural perspectives of future wireless base stations based on the IBM PowerENâ„¢ processor
Found in: High-Performance Computer Architecture, International Symposium on
By Augusto Vega,Pradip Bose,Alper Buyuktosunoglu,Jeff Derby,Michele Franceschini,Charles Johnson,Robert Montoye
Issue Date:February 2012
pp. 1-10
In wireless networks, base stations are responsible for operating on large amounts of traffic at high speed rates. With the advent of new standards, as 4G, further pressure is put in the hardware requirements to satisfy speeds of up to 1 Gbps. In this work...
 
Energy-Aware Accounting and Billing in Large-Scale Computing Facilities
Found in: IEEE Micro
By Victor Jimenez, Roberto Gioiosa, Francisco J. Cazorla, Mateo Valero, Eren Kursun, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose
Issue Date:May 2011
pp. 60-71
<p>Proposals have focused on reducing energy requirements for large-scale computing facilities (LSCFs), but little research has addressed the need for energy-usage-based accounting. Energy-aware accounting and billing benefits LSCF owners and users. ...
 
Introducing the Adaptive Energy Management Features of the Power7 Chip
Found in: IEEE Micro
By Michael Floyd, Malcolm Allen-Ware, Karthick Rajamani, Bishop Brock, Charles Lefurgy, Alan J. Drake, Lorena Pesantez, Tilman Gloekler, Jose A. Tierno, Pradip Bose, Alper Buyuktosunoglu
Issue Date:March 2011
pp. 60-75
<p>Power7 implements several new adaptive power management techniques which, in concert with the EnergyScale firmware, let it proactively exploit variations in workload, environmental conditions, and overall system use to meet customer-directed power...
 
Abstraction and microarchitecture scaling in early-stage power modeling
Found in: High-Performance Computer Architecture, International Symposium on
By Hans Jacobson, Alper Buyuktosunoglu, Pradip Bose, Emrah Acar, Richard Eickemeyer
Issue Date:February 2011
pp. 394-405
Early-stage, microarchitecture-level power modeling methodologies have been used in industry and academic research for a decade (or more). Such methods use cycle-accurate performance simulators and deduce active power based on utilization markers. A key qu...
 
A case for guarded power gating for multi-core processors
Found in: High-Performance Computer Architecture, International Symposium on
By Niti Madan, Alper Buyuktosunoglu, Pradip Bose, Murali Annavaram
Issue Date:February 2011
pp. 291-300
Dynamic power management has become an essential part of multi-core processors and associated systems. Dedicated controllers with embedded power management firmware are now an integral part of design in such multi-core server systems. Devising a robust pow...
 
Dynamic power gating with quality guarantees
Found in: Low Power Electronics and Design, International Symposium on
By Anita Lungu, Pradip Bose, Alper Buyuktosunoglu, Daniel J. Sorin
Issue Date:August 2009
pp. 377-382
Power gating is usually driven by a predictive control, and frequent mispredictions can counter-productively lead to a large increase in energy consumption. This energy vulnerability could be exploited by malicious applications such as a power virus, or it...
 
Online Estimation of Architectural Vulnerability Factor for Soft Errors
Found in: Computer Architecture, International Symposium on
By Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers
Issue Date:June 2008
pp. 341-352
As CMOS technology scales and more transistors are packed on to the same chip, soft error reliability has become an increasingly important design issue for processors. Prior research has shown that there is significant architecture-level masking, and many ...
 
A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime
Found in: Computer Architecture, International Symposium on
By Jeonghee Shin, Victor Zyuban, Pradip Bose, Timothy M. Pinkston
Issue Date:June 2008
pp. 353-362
Microarchitectural redundancy has been proposed as a means of improving chip lifetime reliability. It is typically used in a reactive way, allowing chips to maintain operability in the presence of failures by detecting and isolating, correcting, and/or rep...
 
Metrics for Architecture-Level Lifetime Reliability Analysis
Found in: Performance Analysis of Systems and Software, IEEE International Symmposium on
By Pradeep Ramachandrany, Sarita V. Adve, Pradip Bose, Jude A. Rivers
Issue Date:April 2008
pp. 202-212
This work concerns metrics for evaluating microarchitectural enhancements to improve processor lifetime reliability. A commonly reported reliability metric is mean time to failure (MTTF). Although the MTTF metric is simpler to evaluate, it does not provide...
 
Evaluating design tradeoffs in on-chip power management for CMPs
Found in: Low Power Electronics and Design, International Symposium on
By Joseph Sharkey, Alper Buyuktosunoglu, Pradip Bose
Issue Date:August 2007
pp. 44-49
In light of the recent shift towards multi-core processor designs, dynamic power-management techniques that were designed for single-core microprocessors must be augmented with larger chip-level control. In this paper, we explore the design-tradeoffs assoc...
 
Thermal-aware task scheduling at the system software level
Found in: Low Power Electronics and Design, International Symposium on
By Jeonghwan Choi, Chen-Yong Cher, Hubertus Franke, Henrdrik Hamann, Alan Weger, Pradip Bose
Issue Date:August 2007
pp. 213-218
In this paper, the impact of thermal effects on low-power repeater insertion methodology is studied. An analytical methodology for thermal-aware repeater insertion that includes the electrothermal coupling between power, delay, and temperature is presented...
 
A Framework for Architecture-Level Lifetime Reliability Modeling
Found in: Dependable Systems and Networks, International Conference on
By Jeonghee Shin, Victor Zyuban, Zhigang Hu, Jude A. Rivers, Pradip Bose
Issue Date:June 2007
pp. 534-543
This paper tackles the issue of modeling chip lifetime reliability at the architecture level. We propose a new and robust structure-aware lifetime reliability model at the architecture-level, where devices only vulnerable to failure mechanisms and the effe...
 
Temperature-limited microprocessors: Measurements and design implications
Found in: VLSI Design, International Conference on
By Hendrik F. Hamann, Alan Weger, James Lacey, Zhigang Hu, Pradip Bose, Erwin Cohen, Jamil Wakil
Issue Date:January 2007
pp. 427-432
The details of the power distribution of state of the art CMOS chips (e.g., local regions of high power (or hotspots), which disproportionally drive up junction temperatures) can have a severe impact on reliability, manufacturing yield and chip performance...
 
An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Canturk Isci, Alper Buyuktosunoglu, Chen-Yong Cher, Pradip Bose, Margaret Martonosi
Issue Date:December 2006
pp. 347-358
Chip-level power and thermal implications will continue to rule as one of the primary design constraints and performance limiters. The gap between average and peak power actually widens with increased levels of core integration. As such, if per-core contro...
 
Looking briefly back, and then forward.
Found in: IEEE Micro
By Pradip Bose
Issue Date:November 2006
pp. 8-9
Pradip Bose recalls economic and technical changes in the hardware sector of the computer industry over his four years as Editor in Chief of <em>IEEE Micro</em>. As he took office in 2003, the frequency wars characteristic of single-core proces...
 
Designing reliable systems with unreliable components
Found in: IEEE Micro
By Pradip Bose
Issue Date:September 2006
pp. 5-6
Many electronics experts predicted that component failures (in particular, tube failures) in the pioneering ENIAC machine would be so frequent that the machine would never be useful. But the engineers (system architects) and component manufacturers improve...
 
Pre-Silicon Modeling and Analysis: Impact On Real Design
Found in: IEEE Micro
By Pradip Bose
Issue Date:July 2006
pp. 3
Micro editor in chief Pradip Bose talks about the challenge of predicting and tuning a microprocessor's net quality well before its tape out and eventual production cycle.
 
Robust On-Chip Communication
Found in: IEEE Micro
By Pradip Bose
Issue Date:May 2006
pp. 5
The balance between computation and communication is a fundamental issue in application performance. As the chip industry gets entrenched in multicore architectures, this issue will become particularly and progressively important--not only in terms of chip...
 
Workload characterization: A key aspect of microarchitecture design
Found in: IEEE Micro
By Pradip Bose
Issue Date:March 2006
pp. 5-6
Micro editor in chief Pradip Bose talks about the issue of workload characterization in the modern setting.
 
Measuring the impact of microarchitectural ideas
Found in: IEEE Micro
By Pradip Bose
Issue Date:January 2006
pp. 5-6
Welcome to <em>IEEE Micro</em>?s first issue of 2006. We are starting this year with our annual Top Picks issue. This is the third such annual collection of magazine-style adaptations of our top-rated papers selected from the past year?s comput...
 
Designing microprocessors with robust functionality and performance
Found in: IEEE Micro
By Pradip Bose
Issue Date:November 2005
pp. 5
The topic of reliability-aware microarchitectures is an emerging area of interest to the microarchitecture R&D community. This issue of <em>IEEE Micro</em> focuses in on that important topic.
 
Presilicon modeling: challenges in the late CMOS era
Found in: IEEE Micro
By Pradip Bose
Issue Date:July 2005
pp. 5-6
<em>IEEE Micro</em> editor in chief Pradip Bose writes that in a future of
 
Exploiting Structural Duplication for Lifetime Reliability Enhancement
Found in: Computer Architecture, International Symposium on
By Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers
Issue Date:June 2005
pp. 520-531
<p>Increased power densities (and resultant temperatures) and other effects of device scaling are predicted to cause significant lifetime reliability problems in the near future. In this paper, we study two techniques that leverage microarchitectural...
 
Integrated microarchitectures
Found in: IEEE Micro
By Pradip Bose
Issue Date:May 2005
pp. 5-6
Trends in CMOS technology point to an era of high-performance microprocessor design in which problems such as power consumption and cooling, deviceand chip-level variability, and hard and soft errors threaten to slow down historically established performan...
 
Lifetime Reliability: Toward an Architectural Solution
Found in: IEEE Micro
By Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers
Issue Date:May 2005
pp. 70-80
As scaling threatens to erode reliability standards, lifetime reliability must become a first-class design constraint. Microarchitectural intervention offers a novel way to manage lifetime reliability without significantly sacrificing cost and performance.
 
Variation-tolerant design
Found in: IEEE Micro
By Pradip Bose
Issue Date:March 2005
pp. 5
As we introduce this year?s Hot Chips theme issue, the frequency slowdown trend that is upon us as a result of the CMOS technology outlook has to be the single major point that stands out. It is not just the per-chip power dissipation envelope that is forc...
 
Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors
Found in: High-Performance Computer Architecture, International Symposium on
By Hans Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor Zyuban, Rick Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel Tendler
Issue Date:February 2005
pp. 238-242
Clock-gating has been introduced as the primary means of dynamic power management in recent high-end commercial microprocessors. The temperature drop resulting from active power reduction can result in additional leakage power savings in future processors....
 
The
Found in: IEEE Micro
By Pradip Bose
Issue Date:January 2005
pp. 5
Welcome to <em>IEEE Micro</em>'s first issue of 2005. Like last year, we begin with a theme issue on Hot Interconnects. In addition to this main theme, the issue also contains two other important articles dealing with mainstream microprocessor ...
 
Computer architecture research: Shifting priorities and newer challenges
Found in: IEEE Micro
By Pradip Bose
Issue Date:November 2004
pp. 5
No summary available.
 
Communication versus Computation
Found in: IEEE Micro
By Pradip Bose
Issue Date:September 2004
pp. 5
No summary available.
 
Integrated Analysis of Power and Performance for Pipelined Microprocessors
Found in: IEEE Transactions on Computers
By Victor Zyuban, David Brooks, Viji Srinivasan, Michael Gschwind, Pradip Bose, Philip N. Strenski, Philip G. Emma
Issue Date:August 2004
pp. 1004-1016
<p><b>Abstract</b>—Choosing the pipeline depth of a microprocessor is one of the most critical design decisions that an architect must make in the concept phase of a microprocessor design. To be successful in today's cost/performance mark...
 
Microarchitectural Techniques for Power Gating of Execution Units
Found in: Low Power Electronics and Design, International Symposium on
By Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor Zyuban, Hans Jacobson, Pradip Bose
Issue Date:August 2004
pp. 32-37
Leakage power is a major concern in current and future microprocessor designs. In this paper, we explore the potential of architectural techniques to reduce leakage through power-gating of execution units. This paper first develops parameterized analytical...
 
Understanding the Energy Efficiency of Simultaneous Multithreading
Found in: Low Power Electronics and Design, International Symposium on
By Yingmin Li, David Brooks, Zhigang Hu, Kevin Skadron, Pradip Bose
Issue Date:August 2004
pp. 44-49
Simultaneous multithreading (SMT) has proven to be an effective method of increasing the performance of microprocessors by extracting additional instruction-level parallelism from multiple threads. In current microprocessor designs, power-efficiency is of ...
 
Editor in Chief's Message: Saving power-Lessons from embedded systems
Found in: IEEE Micro
By Pradip Bose
Issue Date:July 2004
pp. 5-6
No summary available.
 
The Impact of Technology Scaling on Lifetime Reliability
Found in: Dependable Systems and Networks, International Conference on
By Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers
Issue Date:July 2004
pp. 177
The relentless scaling of CMOS technology has provided a steady increase in processor performance for the past three decades. However, increased power densities (hence temperatures) and other scaling effects have an adverse impact on long-term processor li...
 
The Case for Lifetime Reliability-Aware Microprocessors
Found in: Computer Architecture, International Symposium on
By Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers
Issue Date:June 2004
pp. 276
Ensuring long processor lifetimes by limiting failures due to wear-out related hard errors is a critical requirement for all microprocessor manufacturers. We observe that continuous device scaling and increasing temperatures are making lifetime reliability...
 
EIC's Message: General-purpose versus application-specific processors
Found in: IEEE Micro
By Pradip Bose
Issue Date:March 2004
pp. 5
No summary available.
 
EIC's Message: Chip-level microarchitecture trends
Found in: IEEE Micro
By Pradip Bose
Issue Date:March 2004
pp. 5
No summary available.
 
New Challenges and Burning Issues
Found in: IEEE Micro
By Pradip Bose
Issue Date:January 2004
pp. 5
<p></p>
 
Dynamically Tuning Processor Resources with Adaptive Processing
Found in: Computer
By David H. Albonesi, Rajeev Balasubramonian, Steven G. Dropsho, Sandhya Dwarkadas, Eby G. Friedman, Michael C. Huang, Volkan Kursun, Grigorios Magklis, Michael L. Scott, Greg Semeraro, Pradip Bose, Alper Buyuktosunoglu, Peter W. Cook, Stanley E. Schuster
Issue Date:December 2003
pp. 49-58
<p>The <em>adaptive processing approach</em> improves microprocessor energy efficiency by dynamically tuning major resources during execution to better match varying application needs. This tuning usually involves reducing a resource's si...
 
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