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Displaying 1-6 out of 6 total
Demystifying multicore throughput metrics
Found in: IEEE Computer Architecture Letters
By Pierre Michaud
Issue Date:July 2013
pp. 63-66
Several different metrics have been proposed for quantifying the throughput of multicore processors. There is no clear consensus about which metric should be used. Some studies even use several throughput metrics. We show that there exists a relation betwe...
Exploiting the Cache Capacity of a Single-Chip Multi-Core Processor with Execution Migration
Found in: High-Performance Computer Architecture, International Symposium on
By Pierre Michaud
Issue Date:February 2004
pp. 186
We propose to modify a conventional single-chip multicore so that a sequential program can migrate from one core to another automatically during execution. The goal of execution migration is to take advantage of the overall onchip cache capacity. We introd...
Data-Flow Prescheduling for Large Instruction Windows in Out-of-Order Processors
Found in: High-Performance Computer Architecture, International Symposium on
By Pierre Michaud, André Seznec
Issue Date:January 2001
pp. 0027
Abstract: The performance of out-of-order processors increases with the instruction window size. In conventional processors, the effective instruction window cannot be larger than the issue buffer. Determining which instructions from the issue buffer can b...
Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors
Found in: Parallel Architectures and Compilation Techniques, International Conference on
By Pierre Michaud, Andre Seznec, Stephan Jourdan
Issue Date:October 1999
pp. 2
The effective performance of wide-issue superscalar processors depends on many parameters, such as branch prediction accuracy, available instruction-level parallelism, and instruction-fetch bandwidth. This paper explores the relations between some of these...
Selecting benchmark combinations for the evaluation of multicore throughput
Found in: 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)
By Ricardo A. Velasquez,Pierre Michaud,Andre Seznec
Issue Date:April 2013
pp. 173-182
Most high-performance processors today are able to execute multiple threads of execution simultaneously. Threads share processor resources, like the last-level cache, which may decrease throughput in a non obvious way, depending on threads' characteristics...
Trading Conflict and Capacity Aliasing in Conditional Branch Predictors
Found in: Computer Architecture, International Symposium on
By André Seznec, Richard Uhlig, Pierre Michaud
Issue Date:June 1997
pp. 292
As modern microprocessors employ deeper pipelines and issue multiple instructions per cycle, they are becoming increasingly dependent on accurate branch prediction. Because hardware resources for branch-predictor tables are invariably limited, it is not po...