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Displaying 1-8 out of 8 total
Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics
Found in: IEEE Transactions on Computers
By Sylvain Guilley, Laurent Sauvage, Florent Flament, Vinh-Nga Vong, Philippe Hoogvorst, Renaud Pacalet
Issue Date:September 2010
pp. 1250-1263
Cryptographic circuits are nowadays subject to attacks that no longer focus on the algorithm but rather on its physical implementation. Attacks exploiting information leaked by the hardware implementation are called side-channel attacks (SCAs). Among these...
 
Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks
Found in: IEEE Transactions on Computers
By Sylvain Guilley, Laurent Sauvage, Philippe Hoogvorst, Renaud Pacalet, Guido Marco Bertoni, Sumanta Chaudhuri
Issue Date:November 2008
pp. 1482-1497
Power-constant logic styles are promising solutions to counter-act side-channel attacks on sensitive cryptographic devices. Recently, one vulnerability has been identified in a standard-cell based power-constant logic called WDDL. Another logic, nicknamed ...
 
Place-and-route impact on the security of DPL designs in FPGAs
Found in: Hardware-Oriented Security and Trust, IEEE International Workshop on
By Sylvain Guilley, Sumanta Chaudhuri, Laurent Sauvage, Tarik Graba, Jean-Luc Danger, Philippe Hoogvorst, Vinh-Nga Vong, Maxime Nassar
Issue Date:June 2008
pp. 26-32
Straightforward implementations of cryptographic algorithms are known to be vulnerable to attacks aimed not at the mathematical structure of the cipher but rather at the weak points of the electronic devices which implement it. These attacks, known as side...
 
Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors
Found in: IEEE Design and Test of Computers
By Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Renaud Pacalet, Yves Mathieu
Issue Date:November 2007
pp. 546-555
This article presents a comprehensive back-end design flow that enables the realization of constant-power cryptoprocessors, natively protected against side-channel attacks exploiting the instant power consumption. The proposed methodology is based on a ful...
 
CMOS Structures Suitable for Secured Hardware
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet, Jean Provost
Issue Date:February 2004
pp. 21414
Unsecured electronic circuits leak physical syndromes correlated to the data they handle. Side-channels attacks, like SPA or DPA, exploit this information leakage. We provide balanced and memoryless CMOS structures for a 2-input secured NAND gate.
   
An 8x8 run-time reconfigurable FPGA embedded in a SoC
Found in: Proceedings of the 45th annual conference on Design automation (DAC '08)
By Florent Flament, Jean-Luc Danger, Philippe Hoogvorst, Sumanta Chaudhuri, Sylvain Guilley
Issue Date:June 2008
pp. 1-30
This paper presents a RTR FPGA embedded in a System on Chip fabricated in 130nm CMOS process. Various aspects of the design flow, from automation to floor-planning are discussed. We explain the measures taken in the FPGA design to guarantee RTR functionali...
     
Efficient tiling patterns for reconfigurable gate arrays
Found in: Proceedings of the 2008 international workshop on System level interconnect prediction (SLIP '08)
By Jean-Luc Danger, Philippe Hoogvorst, Sumanta Chaudhuri, Sylvain Guilley
Issue Date:April 2008
pp. 24-31
In this paper we present a few potentially efficient tiling patterns for gate-array realizations. We start with a brief recapitulation of tiling patterns, and fundamental limits of placement/routing in a two-dimensional plane. We state the first principles...
     
Efficient tiling patterns for reconfigurable gate arrays
Found in: Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays (FPGA '08)
By Jean-Luc Danger, Philippe Hoogvorst, Sumanta Chaudhuri, Sylvain Guilley
Issue Date:February 2008
pp. 1-89
This article does a purely mathematical analysis based on generic models, and the idea is to investigate the possibility of using tiling patterns other than Manhattan grid in FPGAs. The goal of our research is to evolve FPGA architectures with advances in ...
     
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