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Displaying 1-45 out of 45 total
Cache-In-Memory
Found in: Innovative Architecture for Future Generation High-Performance Processors and Systems, International Workshop on
By Jason T. Zawodny, Peter M. Kogge
Issue Date:January 2001
pp. 0003
Abstract: The new technology of Processing-In-Memory now allows relatively large DRAM memory macros to be positioned on the same die with processing logic. Despite the high bandwidth and low latency possible with such macros, more of both is always better....
 
System Reliabilities When Using Triple Modular Redundancy in Quantum-Dot Cellular Automata
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Timothy J. Dysart, Peter M. Kogge
Issue Date:October 2008
pp. 72-80
Nanoelectronic systems are extremely likely to demonstrate high defect and fault rates.??As a result, defect and/or fault tolerance may be necessary at several levels throughout the system. Methods for improving defect tolerance, in order to prevent faults...
 
An Exploration of the Technology Space for Multi-Core Memory/Logic Chips for Highly Scalable Parallel Systems
Found in: Innovative Architecture for Future Generation High-Performance Processors and Systems, International Workshop on
By Peter M. Kogge
Issue Date:January 2005
pp. 55-64
Chip-level multi-processing, where more than one CPU
 
A Microserver View of HTMT
Found in: Parallel and Distributed Processing Symposium, International
By Lilia V. Yerosheva, Shannon K. Kuntz, Jay B. Brockman, Peter M. Kogge
Issue Date:April 2001
pp. 10003b
HTMT is an ambitious new architecture combining cutting edge technologies to reach petaflop performance sooner than current technology trends allow. It is a massively parallel architecture with multi-threaded hardware and a multi-level memory hierarchy. Mi...
 
Quantum-Dot Cellular Automata (QCA) Circuit Partitioning: Problem Modeling and Solutions
Found in: Design Automation Conference
By Dominic A. Antonelli, Danny Z. Chen, Timothy J. Dysart, Xiaobo S. Hu, Andrew B. Kahng, Peter M. Kogge, Richard C. Murphy, Michael T. Niemier
Issue Date:June 2004
pp. 363-368
This paper presents the Quantum-Dot Cellular Automata (QCA) physical design problem, in the context of the VLSI physical design problem. The problem is divided into three subproblems: partitioning, placement, and routing of QCA circuits. This paper present...
 
Trading Bandwidth for Latency: Managing Continuations Through a Carpet Bag Cache
Found in: Innovative Architecture for Future Generation High-Performance Processors and Systems, International Workshop on
By Richard C. Murphy, Peter M. Kogge
Issue Date:January 2002
pp. 41
Processing-In-Memory (PIM) circumvents the von Neumann bottleneck by combining logic and memory (typically DRAM) on a single die. This work examines the performance of a mobile thread execution model in which threads traverse the system?s address space in ...
 
Of Piglets and Threadlets: Architectures for Self-Contained, Mobile, Memory Programming
Found in: Innovative Architecture for Future Generation High-Performance Processors and Systems, International Workshop on
By Peter M. Kogge
Issue Date:January 2004
pp. 130-138
Virtually all of the discussion on
 
[2010] Facing the Exascale Energy Wall
Found in: 2010 International Workshop on Innovative Architecture for Future-Generation High-Performance Processors and Systems (IWIA)
By Peter M. Kogge,Patrick La Fratta,Megan Vance
Issue Date:January 2010
pp. 51-58
A recent report focused on the technical challengesin advancing from today's
 
Yield Estimation of Molecular QCA Memory Structures with Geometric Analysis
Found in: Design and Test of Nano Devices, Circuits and Systems, IEEE International Workshop on
By Timothy J. Dysart, Daniel J. Lohmer, Peter M. Kogge
Issue Date:September 2008
pp. 45-48
Nanoelectronic devices and circuits are likely to contain multiple defects and exhibit faulty behavior, especially as larger circuits are built.??In this work, we will present a new method for estimating the yield of memory structures constructed from mole...
 
Probabilistic Analysis of a Molecular Quantum-Dot Cellular Automata Adder
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Timothy J. Dysart, Peter M. Kogge
Issue Date:September 2007
pp. 478-486
Since nanoelectronic devices are likely to be defective and error-prone, developing an understanding of circuit reliabilities and critical components will be required. To this end, this paper examines reliability considerations of several sample circuits w...
 
EXECUBE-A New Architecture for Scaleable MPPs
Found in: Parallel Processing, International Conference on
By Peter M. Kogge
Issue Date:August 1994
pp. 77-84
The EXECUBE chip is a new single part type building block for MPP systems that scales seamlessly from a few chips (with a few hundred mips) to thousands of chips with petaop potential. Further, the chip architecture supports directly both SIMD and MIMD mod...
 
Comparing the Reliability of PLA and Custom Logic Implementations of a QCA Adder
Found in: Design and Test of Nano Devices, Circuits and Systems, IEEE International Workshop on
By Timothy J. Dysart, Peter M. Kogge
Issue Date:September 2008
pp. 53-56
Assuming that nanoelectronic systems will face a large number of defective devices resulting in numerous computational faults, defect and/or fault tolerance will be necessary in these systems.??However, multiple methods exist for providing this tolerance; ...
 
Recomposing an Irregular Algorithm Using a Novel Low-Level PGAS Model
Found in: Parallel Processing Workshops, International Conference on
By Megan Cason,Peter M. Kogge
Issue Date:September 2011
pp. 238-248
This paper presents analysis and simulation results for a toolkit of parallel graph traversal primitives which were built using a novel, low-level partitioned global address space (PGAS) programming model. Unlike high-level HEC PGAS languages (UPC, Chapel,...
 
The Challenges of Petascale Architectures
Found in: Computing in Science and Engineering
By Peter M. Kogge
Issue Date:September 2009
pp. 10-16
<p>In 2008, the first petaflops systems went into operation. Such systems will eventually mature into petascale systems capable of 1,000 times more general computation than robust terascale systems. To achieve this, we need architectures that are ine...
 
Using Circuits and Systems-Level Research to Drive Nanotechnology
Found in: Computer Design, International Conference on
By Michael T. Niemier, Ramprasad Ravichandran, Peter M. Kogge
Issue Date:October 2004
pp. 302-309
This paper details nano-scale devices being researched by physical scientists to build computational systems. It also reviews some existing system design work that uses the devices to be discussed. It concludes with a discussion of how the authors believe ...
 
Inherently Lower-Power High-Performance Superscalar Architectures
Found in: IEEE Transactions on Computers
By Victor V. Zyuban, Peter M. Kogge
Issue Date:March 2001
pp. 268-285
<p><b>Abstract</b>—In recent years, reducing power has become an important design goal for high-performance microprocessors. This work attempts to bring the power issue to the earliest phases of microprocessor development, in particular, ...
 
Using the TOP500 to trace and project technology and architecture trends
Found in: SC Conference
By Peter M. Kogge,Timothy J. Dysart
Issue Date:November 2011
pp. 1-11
The TOP500 is a treasure trove of information on the leading edge of high performance computing. It was used in the 2008 DARPA Exascale technology report to isolate out the effects of architecture and technology on high performance computing, and lay the g...
 
Modeling bounds on migration overhead for a traveling thread architecture
Found in: Parallel and Distributed Processing Workshops and PhD Forum, 2011 IEEE International Symposium on
By Patrick A. La Fratta,Peter M. Kogge
Issue Date:April 2010
pp. 1-8
Heterogeneous multicore architectures have gained widespread use in the general purpose and scientific computing communities, and architects continue to investigate techniques for easing the burden of parallelization from the programmer. This paper present...
 
An Exploration of Tiled Architectures for Space Applications
Found in: Space Mission Challenges for Information Technology, IEEE International Conference on
By Peter M. Kogge, Megan Vance
Issue Date:July 2009
pp. 3-12
For many reasons, the chip technology for spacecraft computing has lagged commercial systems by decades. Equally disconcerting, however, has been a similar lag in the computer architectures used. This paper will look at an emerging class of multi-core proc...
 
On the Memory Access Patterns of Supercomputer Applications: Benchmark Selection and Its Implications
Found in: IEEE Transactions on Computers
By Richard C. Murphy, Peter M. Kogge
Issue Date:July 2007
pp. 937-945
This paper compares the System Performance Evaluation Cooperative (SPEC) Integer and Floating-Point suites to a set of real-world applications for high-performance computing at Sandia National Laboratories. These applications focus on the high-end scientif...
 
Redundancy in Multi-core Memory-Rich Application-Specific PIM Chips
Found in: Innovative Architecture for Future Generation High-Performance Processors and Systems, International Workshop on
By Peter M. Kogge, Jay B. Brockman
Issue Date:January 2006
pp. 13-20
A trend of growing significance in the arena of advanced microprocessor chip design is the inclusion of multiple processor cores onto the same die with significant parts of the memory hierarchy. This is done to reduce both non-recurring design costs and po...
 
Lightweight Chip Multi-Threading (LCMT): Maximizing Fine-Grained Parallelism On-Chip
Found in: IEEE Transactions on Parallel and Distributed Systems
By Sheng Li, Shannon Kuntz, Jay B. Brockman, Peter M. Kogge
Issue Date:July 2011
pp. 1178-1191
Irregular and dynamic applications, such as graph problems and agent-based simulations, often require fine-grained parallelism to achieve good performance. However, current multicore processors only provide architectural support for coarse-grained parallel...
 
[2009] Exploring the Possible Past Futures of a Single Part Type Multi-core PIM Chip
Found in: 2010 International Workshop on Innovative Architecture for Future-Generation High-Performance Processors and Systems (IWIA)
By Peter M. Kogge
Issue Date:January 2010
pp. 30-38
Execube, a chip built in 1993, was most probablythe world's first true multi-core microprocessor, the world's first Processing-In-Memory chip built on a DRAM process, and oneof the earliest attempts to build a single part type chip out ofwhich larger paral...
 
The Shape of Things to Come: Future Potential of
Found in: Innovative Architecture for Future Generation High-Performance Processors and Systems, International Workshop on
By Peter M. Kogge
Issue Date:January 2008
pp. 3-10
The Top 500 list has been tracking supercomputers since the early 1990s. The bulk of those systems, especially recently, have been built from leading edge commodity microprocessors. This paper analyzes potential future characteristics of such systems in th...
 
Some Initial Explorations into the Hierarchical Multi-core Chip Design Space for HPC Systems
Found in: Innovative Architecture for Future Generation High-Performance Processors and Systems, International Workshop on
By Peter M. Kogge
Issue Date:January 2007
pp. 3-10
Multi-core designs have emerged as the dominant trend for commodity and high performance microprocessor chips, in virtually all market segments. This includes the high performance supercomputing arena. Using a particular HPC system as a baseline, this pape...
 
A Comparative Analysis of Power and Energy Management Techniques in Real Embedded Applications
Found in: Innovative Architecture for Future Generation High-Performance Processors and Systems, International Workshop on
By Peter M. Kogge, Arun Rodrigues, Jeffrey Namkung, Nazeeh Aranki, N. Benny Toomarian, Kanad Ghose
Issue Date:July 2003
pp. 2
This paper demonstrates via use of realistic embedded program execution traces, the power and energy savings possible from a variety of dynamic power management techniques. This includes a new variable cluster microarchitecture that allows very dynamic con...
 
From Bits to Chips: A Multidisciplinary Curriculum for Microelectronics System Design Education
Found in: Microelectronics Systems Education, IEEE International Conference on/Multimedia Software Engineering, International Symposium on
By Gary H. Bernstein, Jay B. Brockman, Peter M. Kogge, Gregory L. Snider, Barbara E. Walvoord
Issue Date:June 2003
pp. 95
We describe a program in multidisciplinary education of microelectronics systems design at the University of Notre Dame. In the
 
Bouncing Threads: Merging a New Execution Model into a Nanotechnology Memory
Found in: VLSI, IEEE Computer Society Annual Symposium on
By Sarah E. Frost, Arun F. Rodrigues, Charles A. Giefer, Peter M. Kogge
Issue Date:February 2003
pp. 19
The need for small, high speed, low power computers as the end of Moore's law approaches s driving research into nanotechnology. These novel devices have significantly different properties than traditional MOS devices and require new design methodologies, ...
 
Exploring and Exploiting Wire-Level Pipelining in Emerging Technologies
Found in: Computer Architecture, International Symposium on
By Michael Thaddeus Niemier, Peter M. Kogge
Issue Date:July 2001
pp. 0166
Abstract: Pipelining is a technique that has long since been considered fundamental by computer architects. However, the world of nanoelectronics is pushing the idea of pipelining to new and lower levels--particularly the device level. How this affects cir...
 
PIM Architectures to Support Petaflops Level Computation in the HTMT Machine
Found in: Innovative Architecture for Future Generation High-Performance Processors and Systems, International Workshop on
By Peter M. Kogge, Jay B. Brockman, Vincent W. Freeh
Issue Date:November 1999
pp. 35
The HTMT project is an ambitious attempt to combine a variety of emerging technologies into a petaflops-level computing system available many years before an equivalent machine can be built from current technologies. One of the key problems in such archite...
 
Logic in Wire: Using Quantum Dots to Implement a Microprocessor
Found in: Great Lakes Symposium on VLSI
By Michael T. Niemier, Peter M. Kogge
Issue Date:March 1999
pp. 118
Despite the seemingly endless upwards spiral of modern VLSI technology, many experts are predicting a hard wall for CMOS in about a decade. Given this, researchers continue to look at alternative technologies, one of which is based on quantum dots, called ...
 
The
Found in: VLSI, IEEE Computer Society Annual Symposium on
By Michael T. Niemier, Peter M. Kogge
Issue Date:February 2004
pp. 3
One of the key problems in bringing nanotechnology to commercial reality is in finding design methodologies that permit such devices to be combined into computationally useful circuits with favorable density gains over ACMOS, but with minimum assembly comp...
 
The State of State
Found in: High-Performance Computer Architecture, International Symposium on
By Peter M. Kogge
Issue Date:February 2003
pp. 266
No summary available.
   
A Design of and Design Tools for a Novel Quantum Dot Based Microprocessor
Found in: Design Automation Conference
By Michael J. Kontz, Peter M. Kogge, Michael T. Niemier
Issue Date:June 2000
pp. 227-232
Despite the seemingly endless upwards spiral of modern VLSI technology, many experts are predicting a hard wall for CMOS in about a decade. Given this, researchers continue to look at alternative technologies, one of which is based on quantum dots, called ...
 
Introducing mNUMA: an extended PGAS architecture
Found in: Proceedings of the Fourth Conference on Partitioned Global Address Space Programming Model (PGAS '10)
By Megan Vance, Peter M. Kogge
Issue Date:October 2010
pp. 1-10
We describe design details of a Light Weight Processing migration-NUMA architecture, a novel high performance system design that provides hardware support for a partitioned global address space, migrating subjects, and word level synchronization primitives...
     
Organizing wires for reliability in magnetic QCA
Found in: ACM Journal on Emerging Technologies in Computing Systems (JETC)
By Peter M. Kogge, Timothy J. Dysart
Issue Date:November 2009
pp. 1-10
This article investigates, via analytic modeling, how a magnetic QCA wire should be organized to provide the highest reliability. We compare a nonredundant wire and two redundant wire organizations. For all three organizations, a fault rate per unit length...
     
General floorplan for reversible quantum-dot cellular automata
Found in: Proceedings of the 4th international conference on Computing frontiers (CF '07)
By Erik P. DeBenedictis, Peter M. Kogge, Sarah E. Frost-Murphy
Issue Date:May 2007
pp. 77-82
This paper presents the Collapsed Bennett Layout, a general purpose floorplan for reversible quantum-dot cellular automata (QCA) circuits. In order to exploit the full density and speed potential of emerging nanodevices, the principles of reversible comput...
     
Reversible computation with quantum-dot cellular automata (QCA)
Found in: Proceedings of the 2nd conference on Computing frontiers (CF '05)
By Craig S. Lent, Peter M. Kogge, Sarah E. Frost
Issue Date:May 2005
pp. 403-403
Quantum-dot cellular automata (QCA) is a strategy in which binary data is represented by charge configuration within a multi-dot cell. Data is transmitted to nearest neighbors by the Coulombic interaction. An electric field acts as a clock and imposes dire...
     
A low cost, multithreaded processing-in-memory system
Found in: Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture (WMPI '04)
By Jay B. Brockman, Peter M. Kogge, Shannon K. Kuntz, Shyamkumar Thoziyoor
Issue Date:June 2004
pp. 16-22
This paper discusses die cost vs. performance tradeoffs for a PIM system that could serve as the memory system of a host processor. For an increase of less than twice the cost of a commodity DRAM part, it is possible to realize a performance speedup of nea...
     
Energy: efficient instruction dispatch buffer design for superscalar processors
Found in: Proceedings of the 2001 international symposium on Low power electronics and design (ISLPED '01)
By Dimitry V. Ponomarev, Gurhan Kucuk, Kanad Ghose, Peter M. Kogge
Issue Date:August 2001
pp. 237-242
Wireless communications and more specifically, the fast growing penetration of cellular phones and cellular infrastructure are the major drivers for the development of new programmable Digital Signal Processors (DSPs). In this tutorial, an overview will be...
     
Exploring and exploiting wire-level pipelining in emerging technologies
Found in: Proceedings of the 28th annual international symposium on Computer architecture (ISCA '01)
By Michael Thaddeus Niemier, Peter M. Kogge
Issue Date:June 2001
pp. 125-131
Pipelining is a technique that has long since been considered fundamental by computer architects. However, the world of nanoelectronics is pushing the idea of pipelining to new and lower levels --- particularly the device level. How this affects circuits a...
     
A design of and design tools for a novel quantum dot based microprocessor
Found in: Proceedings of the 37th conference on Design automation (DAC '00)
By Michael J. Kontz, Michael T. Niemier, Peter M. Kogge
Issue Date:June 2000
pp. 227-232
Despite the seemingly endless upw ards spiral of modern VLSI technology, many experts are predicting a hard w all for CMOS in about a decade. Given this, researc hers con tin ue to look at alternative technologies, one of which is based on quan tumdots, ca...
     
Microservers: a new memory semantics for massively parallel computing
Found in: Proceedings of the 13th international conference on Supercomputing (ICS '99)
By Jay B. Brockman, Peter M. Kogge, Shannon K. Kuntz, Thomas L. Sterling, Vincent W. Freeh
Issue Date:June 1999
pp. 454-463
To minimize the amount of computation and storage for parallel sparse factorization, sparse matrices have to be reordered prior to factorization. We show that none of the popular ordering heuristics proposed before, namely, mulitple minimum degree and nest...
     
The microprogramming of pipelined processors
Found in: Proceedings of the 4th annual symposium on Computer architecture (ISCA '77)
By Peter M. Kogge
Issue Date:March 1977
pp. 217-218
A pipelined processor is one whose computational capabilities are divided into several sequential stages, each of which may be working with an independent set of data at the same instant of time. Such processors are capable of handling large streams of dat...
     
Maximal rate pipelined solutions to recurrence problems
Found in: Proceedings of the 1st annual symposium on Computer architecture (ISCA '73)
By Peter M. Kogge
Issue Date:December 1973
pp. 217-218
An m thorder recurrence problem is defined as the computation of X1, . . . XN, where Xi&equil;f (&abarbelowi, Xi-1, . . Xi-m) and &abarbelow;&abarbelow;i is a set of parameters. On a pipelined computer, where the total stage delay in computing f is df time...
     
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