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Displaying 1-6 out of 6 total
Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault Injections
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By P. Maistri, P. Vanhauwaert, R. Leveugle
Issue Date:September 2007
pp. 499-507
Some protection techniques had been previously proposed for encryption blocks and applied to an AES encryption IP described at RT Level. One of these techniques had been validated by purely functional fault injections (i.e. algorithmic-level fault injectio...
 
A Novel Double-Data-Rate AES Architecture Resistant against Fault Injection
Found in: Fault Diagnosis and Tolerance in Cryptography, Workshop on
By P. Maistri, P. Vanhauwaert, R. Leveugle
Issue Date:September 2007
pp. 54-61
Several techniques have been proposed for encryption blocks in order to provide protection against faults. These techniques usually exploit some form of redundancy, e.g. by means of error detection codes. However, protection schemes that offer an acceptabl...
 
Countermeasures against fault attacks: The good, the bad, and the ugly
Found in: On-Line Testing Symposium, IEEE International
By P. Maistri
Issue Date:July 2011
pp. 134-137
Hardware implementations of cryptographic systems are becoming common, due to new market needs and to reduced costs. However, the security of a system may be seriously compromised by implementation attacks, such as side channel analysis or fault analysis. ...
 
Incorporating Error Detection and Online Reconfiguration into a Regular Architecture for the Advanced Encryption Standard
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By L. Breveglieri, I. Koren, P. Maistri
Issue Date:October 2005
pp. 72-80
<p>Fault injection based attacks on cryptographic devices aim at recovering the secret keys by inducing an error in the computation process. They are now considered a real threat and countermeasures against them must be taken. In this paper, we descr...
 
Towards automated fault pruning with Petri Nets
Found in: On-Line Testing Symposium, IEEE International
By P. Maistri, R. Leveugle
Issue Date:June 2009
pp. 41-46
Embedded systems design is starting considering dependability issues even for mass-market systems. Soft error consequences must in particular be carefully analyzed. Usually, fault injection campaigns are run to analyze the consequences of transient faults,...
 
A Note on Error Detection in an RSA Architecture by Means of Residue Codes
Found in: On-Line Testing Symposium, IEEE International
By L. Breveglieri, P. Maistri, I. Koren
Issue Date:July 2006
pp. 176-177
Recently, various attacks have been proposed against many cryptosystems, exploiting deliberate error injection during the computation process. In this paper, we add a residue-based error detection scheme to an RSA architecture to protect against such attac...
   
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