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Displaying 1-42 out of 42 total
Agri-Food Traceability Management using a RFID System with Privacy Protection
Found in: Advanced Information Networking and Applications, International Conference on
By P. Bernardi, C. Demartini, F. Gandino, B. Montrucchio, M. Rebaudengo, E.R. Sanchez
Issue Date:May 2007
pp. 68-75
In this paper an agri-food traceability system based on public key cryptography and Radio Frequency Identification (RFID) technology is proposed. In order to guarantee safety in food, an efficient tracking and tracing system is required. RFID devices allow...
 
Evaluating Alpha-induced soft errors in embedded microprocessors
Found in: On-Line Testing Symposium, IEEE International
By P. Rech, S. Gerardin, A. Paccagnella, P. Bernardi, M. Grosso, M. Sonza Reorda, D. Appello
Issue Date:June 2009
pp. 69-74
This paper presents the results of Alpha Single Event Upsets tests of an embedded 8051 microprocessor. Cross sections for the different memory resources (i.e., internal registers, code RAM, and user memory) are reported as well as the error rate for differ...
 
DfT Reuse for Low-Cost Radiation Testing of SoCs: A Case Study
Found in: VLSI Test Symposium, IEEE
By D. Appello, P. Bernardi, S. Gerardin, M. Grosso, A. Paccagnella, P. Rech, M. Sonza Reorda
Issue Date:May 2009
pp. 276-281
This paper proposes an efficient low-cost strategy for collecting data during radiation experiments on Systems-on-Chips (SoCs), exploiting the available on-chip Design for Testability (DfT) structures devised for manufacturing test.The approach combines ha...
 
On the Automation of the Test Flow of Complex SoCs
Found in: VLSI Test Symposium, IEEE
By D. Appello, V. Tancorre, P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda
Issue Date:May 2006
pp. 166-171
Modern Systems-on-Chip (SoCs) allow integrating many different functional cores in the same piece of silicon. Their test requires to take fast decisions in the selection of structures and strategies at different stages of the design flow: early computation...
 
On-Line Detection of Control-Flow Errors in SoCs by Means of an Infrastructure IP Core
Found in: Dependable Systems and Networks, International Conference on
By P. Bernardi, L. Bolzani, M. Rebaudengo, M. Sonza Reorda, F. Vargas, M. Violante
Issue Date:July 2005
pp. 50-58
In sub-micron technology circuits high integration levels coupled with the increased sensitivity to soft errors even at ground level make the task of guaranteeing systems? dependability more difficult than ever. In this paper we present a new approach to d...
 
Peak Power Estimation: A Case Study on CPU Cores
Found in: 2012 21st Asian Test Symposium (ATS)
By P. Bernardi,M. De Carvalho,E. Sanchez,M. Sonza Reorda,A. Bosio,L. Dilillo,P. Girard,M. Valka
Issue Date:November 2012
pp. 167-172
High peak power consumption during test may lead to yield loss. On the other hand, reducing too much test power may lead to test escape. In order to overcome this problem, test power has to mimic the power consumed during functional mode, being as high as ...
 
On the Modeling of Gate Delay Faults by Means of Transition Delay Faults
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By P. Bernardi,M. Sonza Reorda,A. Bosio,P. Girard,S. Pravossoudovitch
Issue Date:October 2011
pp. 226-232
This paper describes a novel modeling method for Gate Delay Faults. The methodology considers each Gate Delay Fault as equivalent to a set of Transition Delay Faults in the propagation paths of the affected port. The main advantage of using this model is t...
 
An I-IP based approach for the monitoring of NBTI effects in SoCs
Found in: On-Line Testing Symposium, IEEE International
By C. Guardiani, A. Shibkov, A. Brambilla, G. Storti Gajani, D. Appello, F. Piazza, P. Bernardi
Issue Date:June 2009
pp. 15-20
In this paper we present a design for reliability methodology, with the goal of reducing the impact of transistor V<inf>TH</inf> degradation due for example to phenomena such as NBTI. It uses infrastructure IPs (I-IPs) featuring a self compensa...
 
An efficient fault simulation technique for transition faults in non-scan sequential circuits
Found in: Design and Diagnostics of Electronic Circuits and Systems
By A. Bosio, P. Girard, S. Pravossoudovich, P. Bernardi, M. Sonza Reorda
Issue Date:April 2009
pp. 50-55
This paper proposes an efficient technique for transition delay fault coverage measurement in synchronous sequential circuits. The proposed strategy is based on a combination of multi-valued algebra simulation, critical path tracing and deductive fault sim...
 
An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By P. Bernardi, L. Bolzani, M. Rebaudengo, M. Sonza Reorda, M. Violante
Issue Date:October 2005
pp. 445-453
<p>Software Implemented Hardware Fault Tolerance (SIHFT) techniques are able to detect most of the transient and permanent faults during the usual system operations. However, these techniques are not capable to detect some transient faults affecting ...
 
Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA
Found in: Design, Automation and Test in Europe Conference and Exhibition
By M. Bellato, P. Bernardi, D. Bortolato, A. Candelori, M. Ceschia, A. Paccagnella, M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Zambolin
Issue Date:February 2004
pp. 10584
This paper analyses the effects of Single Event Upsets in an SRAM-based FPGA, with special emphasis for the transient faults affecting the configuration memory. Two approaches are combined: from one side, by exploiting the available information and tools d...
 
Analyzing SEU Effects in SRAM-based FPGAs
Found in: On-Line Testing Symposium, IEEE International
By M. Violante, M. Ceschia, M. Sonza Reorda, A. Paccagnella, P. Bernardi, M. Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, A. Candelori
Issue Date:July 2003
pp. 119
Commercial-Off-The-Shelf SRAM-based FPGA devices are becoming of interests for applications where high dependability and low cost are mandatory constraints. This paper proposes a new method for assessing the effects of SEUs in the device configuration memo...
 
A P1500-Compatible Programmable BIST Aapproach for the Test of Embedded Flash Memories
Found in: Design, Automation and Test in Europe Conference and Exhibition
By P. Bernardi, M. Rebaudengo, M. Sonza Reorda, M. Violante
Issue Date:March 2003
pp. 10720
In this paper we present a microprocessor-based approach suitable for embedded flash memory testing in a System-on-a-chip (SOC) environment. The main novelty of the approach is the high flexibility, which guarantees easy exploitation of the same architectu...
 
Test Considerations about the Structured ASIC Paradigm
Found in: 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
By P. Bernardi,M. Grosso
Issue Date:August 2013
pp. 230-231
We present a survey on the academic and industrial structured ASIC practices, especially focusing on the test strategies currently in use. Then, we compare two possible test generation flows, underlining the most critical aspects introduced by the adoption...
 
Automatic Functional Stress Pattern Generation for SoC Reliability Characterization
Found in: European Test Symposium, IEEE
By D. Appello, P. Bernardi, R. Cagliesi, M. Giancarlini, M. Grosso, E. Sanchez, M. Sonza Reorda
Issue Date:May 2009
pp. 93-98
Reliability testing is increasingly used not only to reduce Infant Mortality effects, but also for Reliability Characterization. This paper first discusses the characteristics of the stimuli to be used during Reliability Characterization experiments, and o...
 
A Deterministic Methodology for Identifying Functionally Untestable Path-Delay Faults in Microprocessor Cores
Found in: Microprocessor Test and Verification, International Workshop on
By P. Bernardi, M. Grosso, E. Sanchez, M. Sonza Reorda
Issue Date:December 2008
pp. 103-108
Delay testing is crucial for most microprocessors. Software-Based Self-Test (SBST) methodologies are appealing, but devising effective test programs addressing the true functionally testable paths and assessing their actual coverage are complex tasks. In t...
 
A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions
Found in: VLSI Test Symposium, IEEE
By K. Christou, M.K. Michael, P. Bernardi, M. Grosso, E. Sanchez, M. Sonza Reorda
Issue Date:May 2008
pp. 389-394
This paper presents an innovative approach for the generation of functional programs to test path-delay faults within microprocessors. The proposed method takes advantage of both the gate- and RT-level description of the processor. The former is used to bu...
 
An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By J. Lagos-Benites, D. Appello, P. Bernardi, M. Grosso, D. Ravotto, E. Sánchez, M. Sonza Reorda
Issue Date:September 2007
pp. 291-302
<p>In this paper, a Software-Based Diagnosis (SBD) procedure suitable for SoCs is proposed to tackle the diagnosis of transition-delay faults. The illustrated methodology takes advantage of an initial Software-Based Self-Test (SBST) test set and of t...
 
On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores
Found in: European Test Symposium, IEEE
By P. Bernardi, M. Grosso, E. Sanchez, M. Sonza Reorda
Issue Date:May 2007
pp. 179-184
Delay testing is mandatory for guaranteeing the correct behavior of today?s high-performance microprocessors. Several methodologies have been proposed to tackle this issue resorting to additional hardware or to software self-test techniques. Software techn...
 
An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs
Found in: Design, Automation and Test in Europe Conference and Exhibition
By P. Bernardi, E. Sanchez, M. Schillaci, G. Squillero, M.S. Reorda
Issue Date:March 2006
pp. 90
The ever increasing usage of microprocessor devices is sustained by a high volume production that in turn requires a high production yield, backed by a controlled process. Fault diagnosis is an integral part of the industrial effort towards these goals. Th...
 
Integrating BIST Techniques for On-Line SoC Testing
Found in: On-Line Testing Symposium, IEEE International
By A. Manzone, P. Bernardi, M. Grosso, M. Rebaudengo, E. Sanchez, M. Sonza Reorda
Issue Date:July 2005
pp. 235-240
Today?s complex system-on-chip integrated circuits include a wide variety of functional IPs whose correct manufacturing must be guaranteed by IC producers. Infrastructure IPs are increasingly often inserted to achieve this purpose; such blocks, explicitly ...
 
Exploiting an Infrastructure IP to Reduce the Costs of Memory Diagnosis Costs in SoCs
Found in: European Test Symposium, IEEE
By P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda
Issue Date:May 2005
pp. 202-207
Discriminating between good and faulty chips is often not enough during IC manufacturing phases, where a complete understanding about failure mechanisms is required to ramp up production yield. When considering embedded memories, information about the whol...
 
On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs
Found in: On-Line Testing Symposium, IEEE International
By P. Bernardi, M. Sonza Reorda, L. Sterpone, M. Violante
Issue Date:July 2004
pp. 115
The growing adoption of SRAM-based Field Programmable Gate Arrays (FPGAs) in safety-critical applications demands for efficient methodologies for evaluating their reliability. Single Event Upsets (SEUs) affecting the configuration memory of SRAM-based FPGA...
 
A New Architecture to Cross-Fertilize On-Line and Manufacturing Testing
Found in: Asian Test Symposium
By P. Bernardi,M. Sonza Reorda
Issue Date:November 2011
pp. 142-147
This paper deals with the on-line test of SoCs including cores equipped with BIST circuitry and IEEE 1500 wrappers. A method is proposed, which exploits an Infrastructure IP named OTC to manage the on-line test, the OTC module activates the test and provid...
 
A Hybrid Approach for Detection and Correction of Transient Faults in SoCs
Found in: IEEE Transactions on Dependable and Secure Computing
By P. Bernardi, L.M. Bolzani Poehls, M. Grosso, M. Sonza Reorda
Issue Date:October 2010
pp. 439-445
Critical applications based on Systems-on-Chip (SoCs) require suitable techniques that are able to ensure a sufficient level of reliability. Several techniques have been proposed to improve fault detection and correction capabilities of faults affecting So...
 
An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs
Found in: Design and Diagnostics of Electronic Circuits and Systems
By L. Ciganda, F. Abate, P. Bernardi, M. Bruno, M. Sonza Reorda
Issue Date:April 2009
pp. 258-263
Reducing the cost of test (in particular by reducing its duration and the cost of the required ATE) is a common goal which has largely been pursued in the past, mainly by introducing suitable on chip Design for Testability (DfT) circuitry. Today, the incre...
 
An Innovative and Low-Cost Industrial Flow for Reliability Characterization of SoCs
Found in: European Test Symposium, IEEE
By D. Appello, P. Bernardi, R. Cagliesi, M. Giancarlini, M. Grosso
Issue Date:May 2008
pp. 140-145
This paper describes a novel approach to enhance the process of reliability characterization for VLSI SoC products. To do this, we exploit Design for Test and Diagnosis structures in combination with new low-cost tester features and architecture. The main ...
 
An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers
Found in: Design, Automation and Test in Europe Conference and Exhibition
By P. Bernardi, M. Sonza Reorda
Issue Date:March 2008
pp. 194-199
Low-Cost test methodologies for Systems-on-Chip are increasingly popular. They dictate which features have to be included on-chip and which test procedures have to be adopted in order to guarantee high test quality, while minimizing application costs. Cons...
 
Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study
Found in: Design, Automation and Test in Europe Conference and Exhibition
By P. Bernardi, G. Masera, F. Quaglio, M. Sonza Reorda
Issue Date:March 2005
pp. 228-233
In this paper we describe how we applied a BIST-based approach to the test of a logic core to be included in System-on-a-chip (SoC) environments. The approach advantages are the ability to protect the core IP, the simple test interface (thanks also to the ...
 
Exploiting Programmable BIST For The Diagnosis of Embedded Memory Cores
Found in: Test Conference, International
By D. Appello, P. Bernardi, A. Fudoli, M. Rebaudengo, M. Sonza Reorda, V. Tancorre, M. Violante
Issue Date:October 2003
pp. 379
This paper addresses the issue of testing and diagnosing a memory core embedded in a complex SOC. The proposed solution is based on a P1500-compliant wrapper that follows a programmable BIST approach and is able to support both testing and diagnosis. Exper...
 
An effective methodology for on-line testing of embedded microprocessors
Found in: On-Line Testing Symposium, IEEE International
By P. Bernardi,L. Ciganda,E. Sanchez,M. S. Reorda
Issue Date:July 2011
pp. 270-275
Testing embedded microprocessors at mission time is nowadays a requirement in many SoC applications. In this paper, we introduce a methodology where the detection of operational faults is performed while the normal operations are temporarily suspended, by ...
 
Fault grading of software-based self-test procedures for dependable automotive applications
Found in: 2011 Design, Automation & Test in Europe
By P Bernardi,M Grosso,E Sanchez,O Ballan
Issue Date:March 2011
pp. 1-2
Today, electronic devices are increasingly employed in different fields, including safety- and mission-critical applications, where the quality of the product is an essential requirement. In the automotive field, on-line self-test is a dependability techni...
   
An Enhanced Strategy for Functional Stress Pattern Generation for System-on-Chip Reliability Characterization
Found in: Microprocessor Test and Verification, International Workshop on
By M. de Carvalho, P. Bernardi, E. Sanchez, M. Sonza Reorda
Issue Date:December 2010
pp. 29-34
Reliability characterization is the industrial process intended to measure the useful life period and failure rate of a component population by exploiting stress mechanisms. The paper describes a methodology for the automatic generation of stress programs ...
 
A Fault Grading Methodology for Software-Based Self-Test Programs in Systems-on-Chip
Found in: Microprocessor Test and Verification, International Workshop on
By O. Ballan, P. Bernardi, G. Fontana, M. Grosso, E. Sanchez
Issue Date:December 2010
pp. 43-46
Today, electronic devices are increasingly employed in different fields, including safety- and mission-critical applications, where the quality of the product is an essential requirement. In the automotive field, the Software-Based Self-Test is a dependabi...
 
A Hybrid Approach to Fault Detection and Correction in SoCs
Found in: On-Line Testing Symposium, IEEE International
By P. Bernardi, L. Bolzani, M. Sonza Reorda
Issue Date:July 2007
pp. 107-112
The reliability of Systems-on-Chip (SoCs) is very important with respect to their use in different types of critical applications. Several fault tolerance techniques have been proposed to improve their fault detection and correction capabilities. These app...
 
Extended Fault Detection Techniques for Systems-on-Chip
Found in: Design and Diagnostics of Electronic Circuits and Systems
By P. Bernardi, L. Bolzani, M. Sonza Reorda
Issue Date:April 2007
pp. 1-6
The adoption of Systems-on-Chip (SoCs) in different types of applications represents an attracting solution. However, the high integration level of SoCs increases the sensitivity to transient faults and consequently introduces some reliability concerns. Se...
 
Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications
Found in: Microprocessor Test and Verification, International Workshop on
By P. Bernardi, L. Bolzani, A. Manzone, M. Osella, M. Violante, M. Sonza Reorda
Issue Date:December 2006
pp. 3-8
The adoption of Systems-on-a-Chip (SoCs) in automotive systems opens interesting possibilities, but also introduces significant dependability concerns. Up to now, researchers focused most of their efforts in devising new solutions for improving the dependa...
 
A Pattern Ordering Algorithm for Reducing the Size of Fault Dictionaries
Found in: VLSI Test Symposium, IEEE
By P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda
Issue Date:May 2006
pp. 386-391
Determining the relation between defects and faults (fault diagnosis) in digital circuits is a key concept for semiconductors production yield improvement. Nowadays, fault diagnosis requires heavy computations and large data structures. This paper proposes...
 
Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores
Found in: Microprocessor Test and Verification, International Workshop on
By P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda
Issue Date:November 2005
pp. 55-62
Semiconductor manufacturers aim at delivering new devices within shorter times in order to gain market shares. First silicon debug is an important issue in order to minimize the time-to-market. In this paper we propose an Infrastructure IP (I-IP) intended ...
 
Using Infrastructure IPs to Support SW-Based Self-Test of Processor Cores
Found in: Microprocessor Test and Verification, International Workshop on
By P. Bernardi, M. Rebaudengo, M. Sonza Reorda
Issue Date:September 2004
pp. 22-27
SoCs normally include microprocessor/microcontroller cores. Testing them following the software-based self-test approach is attractive, mainly because this allows at-speed testing, and does not require internally modifying the core. However, this raises so...
 
Exploiting an I-IP for In-Field SOC Test
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By P. Bernardi, M. Rebaudengo, M. Sonza Reorda
Issue Date:October 2004
pp. 404-412
Today's complex system-on-chip integrated circuits include a wide variety of functional IPs whose correct manufacturing must be guaranteed by IC producers. Infrastructure IPs are increasingly often inserted to achieve this purpose; such blocks, explicitly ...
 
An novel methodology for reducing SoC test data volume on FPGA-based testers
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '08)
By M. Sonza Reorda, P. Bernardi
Issue Date:March 2008
pp. 1-30
Low-Cost test methodologies for Systems-on-Chip are increasingly popular. They dictate which features have to be included on-chip and which test procedures have to be adopted in order to guarantee high test quality, while minimizing application costs. Cons...
     
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