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Displaying 1-17 out of 17 total
Performance Per Watt Benefits of Dynamic Core Morphing in Asymmetric Multicores
Found in: Parallel Architectures and Compilation Techniques, International Conference on
By Rance Rodrigues,Arunachalam Annamalai,Israel Koren,Sandip Kundu,Omer Khan
Issue Date:October 2011
pp. 121-130
The trend toward multicore processors is moving the emphasis in computation from sequential to parallel processing. However, not all applications can be parallelized and benefit from multiple cores. Such applications lead to under-utilization of parallel r...
 
Toward Holistic Soft-Error-Resilient Shared-Memory Multicores
Found in: Computer
By Qingchuan Shi,Omer Khan
Issue Date:October 2013
pp. 56-64
A proposed lightweight, soft-error-resilient architecture for shared-memory multicores enables cores to autonomously perform redundant execution of uninterrupted instruction sequences. The distributed redundancy control mechanism operates in concert with t...
 
Low-Latency Mechanisms for Near-Threshold Operation of Private Caches in Shared Memory Multicores
Found in: 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture Workshops (MICROW)
By Farrukh Hijaz,Qingchuan Shi,Omer Khan
Issue Date:December 2012
pp. 68-73
Near-threshold voltage operation is widely acknowledged as a poten- tial mechanism to achieve an order of magnitude reduction in energy consumption in future processors. However, processors cannot operate reliably below a minimum voltage, Vccmin, since har...
 
Time-Predictable Computer Architecture for Cyber-Physical Systems: Digital Emulation of Power Electronics Systems
Found in: Real-Time Systems Symposium, IEEE International
By Michel Kinsy,Omer Khan,Ivan Celanovic,Dusan Majstorovic,Nikola Celanovic,Srinivas Devadas
Issue Date:December 2011
pp. 305-316
The smart grid concept is a good example of a complex cyber-physical system (CPS) that exhibits intricate interplay between control, sensing, and communication infrastructure on one side, and power processing and actuation on the other side. The more exten...
 
Scalable, accurate multicore simulation in the 1000-core era
Found in: Performance Analysis of Systems and Software, IEEE International Symmposium on
By Mieszko Lis, Pengju Ren, Myong Hyon Cho, Keun Sup Shim, Christopher W. Fletcher, Omer Khan, Srinivas Devadas
Issue Date:April 2011
pp. 175-185
We present HORNET, a parallel, highly configurable, cycle-level multicore simulator based on an ingress-queued worm-hole router NoC architecture. The parallel simulation engine offers cycle-accurate as well as periodic synchronization; while preserving fun...
 
Hardware/Software Codesign Architecture for Online Testing in Chip Multiprocessors
Found in: IEEE Transactions on Dependable and Secure Computing
By Omer Khan, Sandip Kundu
Issue Date:September 2011
pp. 714-727
As the semiconductor industry continues its relentless push for nano-CMOS technologies, long-term device reliability and occurrence of hard errors have emerged as a major concern. Long-term device reliability includes parametric degradation that results in...
 
Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors
Found in: IEEE Transactions on Computers
By Omer Khan, Sandip Kundu
Issue Date:May 2010
pp. 651-665
As the semiconductor industry continues its relentless push for nano-CMOS technologies, device reliability and occurrence of hard errors have emerged as a dominant concern in multicores. Although regular memory structures are protected against hard errors ...
 
A framework for predictive dynamic temperature management of microprocessor systems
Found in: Computer-Aided Design, International Conference on
By Omer Khan, Sandip Kundu
Issue Date:November 2008
pp. 258-263
The sustained push for performance, transistor count and instruction level parallelism has reached a point where IC thermal issues are at the forefront of design constraints. Many of the current systems deploy dynamic voltage and frequency scaling (DVFS) t...
 
A HW-SW Multicore Architecture to Tradeoff Program Accuracy and Resilience Overheads
Found in: IEEE Computer Architecture Letters
By Qingchuan Shi,Henry Hoffmann,Omer Khan
Issue Date:February 2015
pp. 1
To protect multicores from soft-error perturbations, resiliency schemes have been developed with high coverage but high power/performance overheads (2). We observe that not all soft-errors affect program correctness, some soft-errors only affect program ac...
 
Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs
Found in: 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)
By Christopher W. Fletchery,Ling Ren,Xiangyao Yu,Marten Van Dijk,Omer Khan,Srinivas Devadas
Issue Date:February 2014
pp. 213-224
Oblivious RAM (ORAM) is an established cryptographic technique to hide a program's address pattern to an untrusted storage system. More recently, ORAM schemes have been proposed to replace conventional memory controllers in secure processor settings to pro...
   
Locality-aware data replication in the Last-Level Cache
Found in: 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)
By George Kurian,Srinivas Devadas,Omer Khan
Issue Date:February 2014
pp. 1-12
Next generation multicores will process massive data with varying degree of locality. Harnessing on-chip data locality to optimize the utilization of cache and network resources is of fundamental importance. We propose a locality-aware selective data repli...
   
Thread Migration Prediction for Distributed Shared Caches
Found in: IEEE Computer Architecture Letters
By Keun Sup Shim,Mieszko Lis,Omer Khan,Srinivas Devadas
Issue Date:January 2014
pp. 1-1
Chip-multiprocessors (CMPs) have become the mainstream parallel architecture in recent years; for scalability reasons, designs with high core counts tend towards tiled CMPs with physically distributed shared caches. This naturally leads to a Non-Uniform Ca...
 
ARCc: A case for an architecturally redundant cache-coherence architecture for large multicores
Found in: Computer Design, International Conference on
By Omer Khan,Henry Hoffmann,Mieszko Lis,Farrukh Hijaz,Anant Agarwal,Srinivas Devadas
Issue Date:October 2011
pp. 411-418
This paper proposes an architecturally redundant cache-coherence architecture (ARCc) that combines the directory and shared-NUCA based coherence protocols to improve performance, energy and dependability. Both coherence mechanisms co-exist in the hardware ...
 
The locality-aware adaptive cache coherence protocol
Found in: Proceedings of the 40th Annual International Symposium on Computer Architecture (ISCA '13)
By George Kurian, Omer Khan, Srinivas Devadas
Issue Date:June 2013
pp. 523-534
Next generation multicore applications will process massive amounts of data with significant sharing. Data movement and management impacts memory access latency and consumes power. Therefore, harnessing data locality is of fundamental importance in future ...
     
A low-overhead dynamic optimization framework for multicores
Found in: Proceedings of the 21st international conference on Parallel architectures and compilation techniques (PACT '12)
By Christopher W. Fletcher, Omer Khan, Rachael Harding, Srinivas Devadas
Issue Date:September 2012
pp. 467-468
This paper argues for a "less is more" design philosophy when integrating dynamic optimization into a multicore system. The primary insight is that dynamic optimization is inherently loosely-coupled and can therefore be supported on multicores with very lo...
     
Brief announcement: distributed shared memory based on computation migration
Found in: Proceedings of the 23rd ACM symposium on Parallelism in algorithms and architectures (SPAA '11)
By Christopher W. Fletcher, Ilia Lebedev, Keun Sup Shim, Michel Kinsy, Mieszko Lis, Myong Hyon Cho, Omer Khan, Srinivas Devadas
Issue Date:June 2011
pp. 253-256
We consider the interactive model of recommender systems, in which users are asked about just a few of their preferences, and in return the system outputs an approximation of all their preferences. The measure of performance is the probe complexity of the ...
     
IT education in a cultural context: a comparison of three approaches in afghanistan
Found in: Proceedings of the 9th ACM SIGITE conference on Information technology education (SIGITE '08)
By Curtis A. Carver, M. Hadi Hedyati, Omer Khan Shaheen
Issue Date:October 2008
pp. 63-68
This paper examines the approaches to information technology (IT) education at three universities in Afghanistan. If the world truly is flat, the approaches to IT education at the National Military Academy of Afghanistan, American University in Kabul, and ...
     
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