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Displaying 1-19 out of 19 total
Fuse: A Technique to Anticipate Failures due to Degradation in ALUs
Found in: On-Line Testing Symposium, IEEE International
By Jaume Abella, Xavier Vera, Osman Unsal, Oguz Ergin, Antonio González
Issue Date:July 2007
pp. 15-22
This paper proposes the fuse, a technique to anticipate failures due to degradation in any ALU (Arithmetic Logic Unit), and particularly in an adder. The fuse consists of a replica of the weakest transistor in the adder and the circuitry required to measur...
 
Defining Wakeup Width for Efficient Dynamic Scheduling
Found in: Computer Design, International Conference on
By Aneesh Aggarwal, Manoj Franklin, Oguz Ergin
Issue Date:October 2004
pp. 36-41
A larger Dynamic Scheduler (DS) exposes more Instruction Level Parallelism (ILP), giving better performance. However, a larger DS also results in a longer scheduler latency and a slower clock speed. In this paper, we propose a new DS design that reduces th...
 
Increasing Processor Performance Through Early Register Release
Found in: Computer Design, International Conference on
By Oguz Ergin, Deniz Balkan, Dmitry Ponomarev, Kanad Ghose
Issue Date:October 2004
pp. 480-487
Modern superscalar microprocessors need sizable register files to support large number of in-flight instructions for exploiting ILP. An alternative to building large register files is to use smaller number of registers, but manage them more effectively. Mo...
 
Distributed Reorder Buffer Schemes for Low Power
Found in: Computer Design, International Conference on
By Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad Ghose
Issue Date:October 2003
pp. 364
We consider two approaches for reducing the complexity and power dissipation in processors that use separate register file to maintain committed register values. The first approach relies on a distributed implementation of the Reorder Buffer (ROB) that spr...
 
Reducing Datapath Energy through the Isolation of Short-Lived Operands
Found in: Parallel Architectures and Compilation Techniques, International Conference on
By Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose
Issue Date:October 2003
pp. 258
We present a technique for reducing the power dissipation in the course of writebacks and committments in a datapath that uses a dedicated architectural register file (ARF) to hold committed values. Our mechanism capitalizes on the observation that most of...
 
A Circuit-Level Implementation of Fast, Energy-Efficient CMOS Comparators for High-Performance Microprocessors
Found in: Computer Design, International Conference on
By Oguz Ergin, Kanad Ghose, Gurhan Kucuk, Dmitry Ponomarev
Issue Date:September 2002
pp. 118
Datapath components in modern high performance superscalar processors employ a significant amount of associative addressing logic based on the use of comparators that dissipate energy on a mismatch. These comparators are used to detect a full match, but as...
 
Exploiting Virtual Addressing for Increasing Reliability
Found in: IEEE Computer Architecture Letters
By Yaman Cakmakci,Oguz Ergin
Issue Date:January 2014
pp. 1-1
A novel method to protect a system against errors resulting from soft errors occurring in the virtual address (VA) storing structures such as translation lookaside buffers (TLB), physical register file (PRF) and the program counter (PC) is proposed in this...
 
Using content-aware bitcells to reduce static energy dissipation
Found in: Computer Design, International Conference on
By Fahrettin Koc,Osman Seckin Simsek,Oguz Ergin
Issue Date:October 2011
pp. 51-56
Static energy dissipation is an increasing problem in contemporary processor design with shrinking feature sizes. Many schemes are proposed to cope with leakage in the literature ranging from using sleep transistors to lowering supply voltage. In this pape...
 
Refueling: Preventing Wire Degradation due to Electromigration
Found in: IEEE Micro
By Jaume Abella, Xavier Vera, Osman S. Unsal, Oguz Ergin, Antonio González, James W. Tschanz
Issue Date:November 2008
pp. 37-46
Electromigration is a major source of wire and via failure. Refueling undoes EM for bidirectional wires and power/ground grids-some of a chip's most vulnerable wires. Refueling exploits EM's self-healing effect by balancing the amount of current flowing in...
 
Reducing Soft Errors through Operand Width Aware Policies
Found in: IEEE Transactions on Dependable and Secure Computing
By Oguz Ergin, Osman S. Unsal, Xavier Vera, Antonio González
Issue Date:July 2009
pp. 217-230
Soft errors are an important challenge in contemporary microprocessors. Particle hits on the components of a processor are expected to create an increasing number of transient errors with each new microprocessor generation. In this paper, we propose simple...
 
Impact of Parameter Variations on Circuits and Microarchitecture
Found in: IEEE Micro
By Osman S. Unsal, James W. Tschanz, Keith Bowman, Vivek De, Xavier Vera, Antonio González, Oguz Ergin
Issue Date:November 2006
pp. 30-39
Parameter variations, which are increasing along with advances in process technologies, affect both timing and power. Variability must be considered at both the circuit and microarchitectural design levels to keep pace with performance scaling and to keep ...
 
Early Register Deallocation Mechanisms Using Checkpointed Register Files
Found in: IEEE Transactions on Computers
By Oguz Ergin, Deniz Balkan, Dmitry Ponomarev, Kanad Ghose
Issue Date:September 2006
pp. 1153-1166
Modern superscalar microprocessors need sizable register files to support a large number of in-flight instructions for exploiting instruction level parallelism (ILP). An alternative to building large register files is to use a smaller number of registers, ...
 
Exploiting Narrow Values for Soft Error Tolerance
Found in: IEEE Computer Architecture Letters
By Oguz Ergin, Osman Unsal, Xavier Vera, Antonio González
Issue Date:July 2006
pp. N/A
Soft errors are an important challenge in contemporary microprocessors. Particle hits on the components of a processor are expected to create an increasing number of transient errors with each new microprocessor generation. In this paper we propose simple ...
 
Power-Efficient Wakeup Tag Broadcast
Found in: Computer Design, International Conference on
By Joseph J. Sharkey, Kanad Ghose, Dmitry V. Ponomarev, Oguz Ergin
Issue Date:October 2005
pp. 654-661
<p>The dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The delay and energy requirement of driving the wakeup tags across the as...
 
Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Oguz Ergin, Deniz Balkan, Kanad Ghose, Dmitry Ponomarev
Issue Date:December 2004
pp. 304-315
A large percentage of computed results have fewer significant bits compared to the full width of a register. We exploit this fact to pack multiple results into a single physical register to reduce the pressure on the register file in a superscalar processo...
 
Energy Efficient Comparators for Superscalar Datapaths
Found in: IEEE Transactions on Computers
By Dmitry V. Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose
Issue Date:July 2004
pp. 892-904
<p><b>Abstract</b>—Modern superscalar datapaths use aggressive execution reordering to exploit instruction-level parallelism. Comparators, either explicit or embedded into content-addressable logic, are used extensively throughout such de...
 
Complexity-Effective Reorder Buffer Designs for Superscalar Processors
Found in: IEEE Transactions on Computers
By Gurhan Kucuk, Dmitry V. Ponomarev, Oguz Ergin, Kanad Ghose
Issue Date:June 2004
pp. 653-665
<p><b>Abstract</b>—All contemporary dynamically scheduled processors support register renaming to cope with false data dependencies. One of the ways to implement register renaming is to use the slots within the Reorder Buffer (ROB) as phy...
 
Isolating Short-Lived Operands for Energy Reduction
Found in: IEEE Transactions on Computers
By Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose
Issue Date:June 2004
pp. 697-709
<p><b>Abstract</b>—A mechanism for reducing the power requirements in processors that use a separate (architectural) register file (ARF) for holding committed values is proposed in this paper. We exploit the notion of short-lived operands...
 
Instruction packing: Toward fast and energy-efficient instruction scheduling
Found in: ACM Transactions on Architecture and Code Optimization (TACO)
By Dmitry V. Ponomarev, Joseph J. Sharkey, Kanad Ghose, Oguz Ergin
Issue Date:June 2006
pp. 156-181
Traditional dynamic scheduler designs use one issue queue entry per instruction, regardless of the actual number of operands actively involved in the wakeup process. We propose Instruction Packing---a novel microarchitectural technique that reduces both de...
     
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