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Displaying 1-50 out of 158 total
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
Found in: Test Conference, International
By Indradeep Ghosh, Niraj K. Jha, Sujit Dey
Issue Date:November 1997
pp. 50
In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has several advantages in terms of time-to-market and system cost, testing such co...
 
Synthesis of Majority and Minority Networks and Its Applications to QCA, TPL and SET Based Nanotechnologies
Found in: VLSI Design, International Conference on
By Rui Zhang, Pallav Gupta, Niraj K. Jha
Issue Date:January 2005
pp. 229-234
In this paper, we present a methodology for efficient majority/minority network synthesis of arbitrary multi-output Boolean functions. Many emerging nanoscale technologies, such as quantum cellular automata (QCA), tunneling phase logic (TPL), and single el...
 
An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Pallav Gupta, Niraj K. Jha
Issue Date:February 2004
pp. 20974
In this paper, we describe an algorithm to post-process a register-transfer level (RTL) architecture to enable gate-level pipelining or nano-pipelining for the nanotechnology based on resonant tunneling diodes (RTDs). Nano-pipelining offers the opportunity...
 
FinFET Logic Circuit Optimization with Different FinFET Styles: Lower Power Possible at Higher Supply Voltage
Found in: 2014 27th International Conference on VLSI Design
By Sourindra Chaudhuri,Niraj K. Jha
Issue Date:January 2014
pp. 476-482
Recently, FinFETs have attracted a lot of attention as a promising alternative to planar transistors, owing to their superior performance, lower leakage, and better tolerance of process variations. FinFETs come in different styles, among which shorted-gate...
 
Evaluation of multiple supply and threshold voltages for low-power FinFET circuit synthesis
Found in: Nanoscale Architectures, IEEE International Symposium on
By Prateek Mishra, Anish Muttreja, Niraj K. Jha
Issue Date:June 2008
pp. 77-84
In modern circuits, power efficiency is a central determinant of circuit efficiency. The exponential increase in the number of transistors in a chip has led to increased chip power dissipation. Therefore, low-power circuits have become a top priority in mo...
 
An Energy-Aware Framework for Coordinated Dynamic Software Management in Mobile Computers
Found in: Modeling, Analysis, and Simulation of Computer Systems, International Symposium on
By Yunsi Fei, Lin Zhong, Niraj K. Jha
Issue Date:October 2004
pp. 306-317
Energy efficiency is a very important and challenging issue for resource-constrained mobile computers. In this paper, we propose a dynamic software management (DSM) framework to improve battery utilization, and avoid competition for limited energy resource...
 
Common-Case Computation: A High-Level Technique for Power and Performance Optimization
Found in: Design Automation Conference
By Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey
Issue Date:June 1999
pp. 56-61
This paper presents a design methodology, called common-case computation (CCC), and new design automation algorithms for optimizing power consumption or performance. The proposed techniques are applicable in conjunction with any high-level design methodolo...
 
Threshold Voltage Control through Multiple Supply Voltages for Power-Efficient FinFET Interconnects
Found in: VLSI Design, International Conference on
By Anish Muttreja, Prateek Mishra, Niraj K. Jha
Issue Date:January 2008
pp. 220-227
In modern circuits, interconnect efficiency is a central determinant of circuit efficiency. Moreover, as technology is scaled down, the importance of efficient interconnect design is increasing. In this paper, we explore an option for low- power interconne...
 
Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha
Issue Date:February 2004
pp. 20904
We propose an algorithm for efficient threshold network synthesis of arbitrary multi-output Boolean functions. The main purpose of this work is to bridge the wide gap that currently exists between research on the development of nanoscale devices and resear...
 
Energy-Efficient Graphical User Interface Design
Found in: IEEE Transactions on Mobile Computing
By Keith S. Vallerio, Lin Zhong, Niraj K. Jha
Issue Date:July 2006
pp. 846-859
Mobile computers, such as cell phones and personal digital assistants (PDAs), have dramatically increased in sophistication. At the same time, the desire of consumers for portability limits battery size. As a result, many researchers have targeted hardware...
 
COFTA: Hardware-Software Co-Synthesis of Heterogeneous Distributed Embedded Systems for Low Overhead Fault Tolerance
Found in: IEEE Transactions on Computers
By Bharat P. Dave, Niraj K. Jha
Issue Date:April 1999
pp. 417-441
<p><b>Abstract</b>—Embedded systems employed in critical applications demand high reliability and availability in addition to high performance. Hardware-software co-synthesis of an embedded system is the process of partitioning, mapping, ...
 
Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems
Found in: Computer-Aided Design, International Conference on
By Le Yan, Jiong Luo, Niraj K. Jha
Issue Date:November 2003
pp. 30
Dynamic voltage scaling (DVS) is a powerful technique for reducing dynamic power consumption in a computing system. However, as technology feature size continues to scale, leakage power is increasing and will limit power savings obtained by DVS alone. Prev...
 
Graceful Degradation in Algorithm-Based Fault Tolerant Multiprocessor Systems
Found in: IEEE Transactions on Parallel and Distributed Systems
By Shalini Yajnik, Niraj K. Jha
Issue Date:February 1997
pp. 137-153
<p><b>Abstract</b>—Algorithm-based fault tolerance (ABFT) is a technique which improves the reliability of a multiprocessor system by providing concurrent error detection and fault location capability to it. It encodes data at the system ...
 
A system-level perspective for efficient NoC design
Found in: Parallel and Distributed Processing Symposium, International
By Amit Kumar, Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha
Issue Date:April 2008
pp. 1-5
With the advent of chip multiprocessors (CMPs) in mainstream systems, the on-chip network that connects different processing cores becomes a critical part of the design. There has been significant work in the recent past on designing these networks for eff...
 
Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level Circuits
Found in: VLSI Test Symposium, IEEE
By Loganathan Lingappan, Niraj K. Jha
Issue Date:May 2005
pp. 418-423
In this paper, we present a novel and accurate method for identifying design for testability (DFT) solutions for register-transfer level (RTL) circuits. In this technique, clauses are generated using a satisfiability (SAT) based automatic test pattern gene...
 
Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications
Found in: Computer-Aided Design, International Conference on
By Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
Issue Date:November 2003
pp. 46
Memory-intensive applications present unique challenges to an ASIC designer in terms of the choice of memory organization, memory size requirements, bandwidth and access latencies, etc. The high potential of single-chip distributed logic-memory architectur...
 
High-level synthesis of distributed logic-memory architectures
Found in: Computer-Aided Design, International Conference on
By Anand Raghunathan, Niraj K. Jha, Srivaths Ravi, Chao Huang
Issue Date:November 2002
pp. 564-571
With the increasing cost of global communication on-chip, high-performance designs for data-intensive applications require architectures that distribute hardware resources (computing logic, memories, interconnect, <i>etc.</i>) throughout a chip...
 
Energy-efficient and Secure Sensor Data Transmission Using Encompression
Found in: 2013 26th International Conference on VLSI Design: concurrently with the 12th International Conference on Embedded Systems
By Meng Zhang,Mehran Mozaffari Kermani,Anand Raghunathan,Niraj K. Jha
Issue Date:January 2013
pp. 31-36
Sensor networks are frequently deployed in physically insecure environments and capture sensitive data, making security a paramount challenge. Cryptographic techniques, such as encryption and hashing, are useful in addressing these concerns. However, the u...
 
Emerging Frontiers in Embedded Security
Found in: 2013 26th International Conference on VLSI Design: concurrently with the 12th International Conference on Embedded Systems
By Mehran Mozaffari Kermani,Meng Zhang,Anand Raghunathan,Niraj K. Jha
Issue Date:January 2013
pp. 203-208
Computing platforms are expected to be deeply embedded within physical objects and people, creating an {\em Internet of Things}. These embedded computing platforms will enable a wide spectrum of applications, including implantable and wearable medical devi...
 
Localized Heating for Building Energy Efficiency
Found in: 2013 26th International Conference on VLSI Design: concurrently with the 12th International Conference on Embedded Systems
By Jun Wei Chuah,Chunxiao Li,Niraj K. Jha,Anand Raghunathan
Issue Date:January 2013
pp. 13-18
Commercial and residential buildings account for a large share of any country's energy consumption (e.g., 40% of total energy consumption in the United States). Within buildings, a major portion of the expended energy is used to provide heating and cooling...
 
Fin Prin: Analysis and Optimization of FinFET Logic Circuits under PVT Variations
Found in: 2013 26th International Conference on VLSI Design: concurrently with the 12th International Conference on Embedded Systems
By Yang Yang,Niraj K. Jha
Issue Date:January 2013
pp. 350-355
Continued scaling of bulk CMOS technology is facing formidable challenges. As an alternative, FinFETs offer a promising solution for the 22nm technology node and beyond though they still suffer from process, voltage, and temperature (PVT) variations. Thus,...
 
A Trusted Virtual Machine in an Untrusted Management Environment
Found in: IEEE Transactions on Services Computing
By Chunxiao Li,Anand Raghunathan,Niraj K. Jha
Issue Date:September 2012
pp. 472-483
Virtualization is a rapidly evolving technology that can be used to provide a range of benefits to computing systems, including improved resource utilization, software portability, and reliability. Virtualization also has the potential to enhance security ...
 
Design of Quantum Circuits for Random Walk Algorithms
Found in: 2012 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
By Amlan Chakrabarti,ChiaChun Lin,Niraj K. Jha
Issue Date:August 2012
pp. 135-140
A quantum algorithm is defined by a sequence of operations that runs on a realistic model of quantum computation. Since the first quantum algorithm proposed by David Deutsch(1985), a large number of impressive quantum algorithms have been developed. Quantu...
 
Accurate Leakage Estimation for FinFET Standard Cells Using the Response Surface Methodology
Found in: VLSI Design, International Conference on
By Sourindra Chaudhuri,Prateek Mishra,Niraj K. Jha
Issue Date:January 2012
pp. 238-244
Among different multi-gate transistors, Fin FETs and Trigate FETs have set themselves apart as the most promising candidates for the upcoming 22nm technology node and beyond owing to their superior device performance, lower leakage power consumption and co...
 
Secure Virtual Machine Execution under an Untrusted Management OS
Found in: Cloud Computing, IEEE International Conference on
By Chunxiao Li, Anand Raghunathan, Niraj K. Jha
Issue Date:July 2010
pp. 172-179
Virtualization is a rapidly evolving technology that can be used to provide a range of benefits to computing systems, including improved resource utilization, software portability, and reliability. For security-critical applications, it is highly desirable...
 
Fault modeling for FinFET circuits
Found in: Nanoscale Architectures, IEEE International Symposium on
By Muzaffer O. Simsir, Ajay Bhoj, Niraj K. Jha
Issue Date:June 2010
pp. 41-46
FinFETs are expected to supplant planar CMOS field-effect transistors (FETs) in the near future, owing to their superior electrical characteristics. From a circuit testing viewpoint, it is unclear if CMOS fault models are comprehensive enough to model all ...
 
NanoV: Nanowire-based VLSI design
Found in: Nanoscale Architectures, IEEE International Symposium on
By Muzaffer O. Simsir, Niraj K. Jha
Issue Date:June 2010
pp. 53-58
In the coming decade, CMOS technology is expected to approach its scaling limitations. Among the proposed nanotechnologies, nanowires have the edge in the size of circuits and logic arrays that have already been fabricated and experimentally evaluated. For...
 
A Secure User Interface for Web Applications Running Under an Untrusted Operating System
Found in: Computer and Information Technology, International Conference on
By Chunxiao Li, Anand Raghunathan, Niraj K. Jha
Issue Date:July 2010
pp. 865-870
Many security-critical web applications, such as online banking and e-commerce, require a secure communication path between the user and a remote server. Securing this endto- end path is challenging and can be broken down into several segments. The network...
 
Token flow control
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Amit Kumar, Li-Shiuan Peh, Niraj K. Jha
Issue Date:November 2008
pp. 342-353
As companies move towards many-core chips, an efficient on-chip communication fabric to connect these cores assumes critical importance. To address limitations to wire delay scalability and increasing bandwidth demands, state-of-the-art on-chip networks us...
 
Toward Ideal On-Chip Communication Using Express Virtual Channels
Found in: IEEE Micro
By Amit Kumar, Li-Shiuan Peh, Partha Kundu, Niraj K. Jha
Issue Date:January 2008
pp. 80-90
Current on-chip networks use a packet-switched design with a complex router at every hop, which imposes significant communication energy, delay, and throughput overhead. We propose reducing energy and delay, and increasing throughput, using express virtual...
 
Fault-Tolerant Computing Using a Hybrid Nano-CMOS Architecture
Found in: VLSI Design, International Conference on
By Muzaffer O. Simsir, Srihari Cadambi, Franjo Ivancic, Martin Roetteler, Niraj K. Jha
Issue Date:January 2008
pp. 435-440
Architectures based on nanoscale molecular devices are at- tracting attention for replacing CMOS architectures at the end of the semiconductor roadmap. The two most promising nan- otechnologies, according to ITRS, are silicon nanowires and carbon nanotubes...
 
Architectural support for safe software execution on embedded processors
Found in: Hardware/software codesign and system synthesis, International conference on
By Niraj K. Jha, Srivaths Ravi, Anand Raghunathan, Divya Arora
Issue Date:October 2006
pp. 106-111
The lack of memory safety in many popular programming languages, including C and C++, has been a cause for great concern in the realm of software reliability, verification, and more recently, system security. A major portion of known security attacks again...
 
Active Learning Driven Data Acquisition for Sensor Networks
Found in: Computers and Communications, IEEE Symposium on
By Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
Issue Date:June 2006
pp. 929-934
Online monitoring of a physical phenomenon over a geographical area is a popular application of sensor networks. Networks representative of this class of applications are typically operated in one of two modes, viz. an always-on mode where every sensor rea...
 
Temperature-Aware On-Chip Networks
Found in: IEEE Micro
By Li Shang, Li-Shiuan Peh, Amit Kumar, Niraj K. Jha
Issue Date:January 2006
pp. 130-139
On-chip networks are becoming increasingly popular as a way to connect high-performance single-chip computer systems, but thermal issues greatly limit network design. This thermal modeling and simulation framework combines with a distributed runtime scheme...
 
Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors
Found in: VLSI Design, International Conference on
By Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha
Issue Date:January 2006
pp. 299-304
<p>Security protocols, such as IPSec and SSL, are being increasingly deployed in the context of networked embedded systems. The resource-constrained nature of embedded systems and, in particular, the modest capabilities of embedded processors make it...
 
Improving the Performance of Automatic Sequential Test Generation by Targeting Hard-to-Test Faults
Found in: VLSI Design, International Conference on
By Loganathan Lingappan, Niraj K. Jha
Issue Date:January 2006
pp. 431-436
Automatic test pattern generation (ATPG) for sequential circuits usually involves search for a sequence of vectors to detect single stuck-at faults. The sequential search space is exponential in the memory elements and primary inputs. Existing sequential t...
 
Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors
Found in: VLSI Design, International Conference on
By Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
Issue Date:January 2006
pp. 473-476
Classical hardware/software partitioning techniques, recent advances in application-specific instruction set architecture (ISA) design tools, etc., provide avenues to address the individual problems of co-processor generation and custom instruction additio...
 
State Encoding of Finite-State Machines Targeting Threshold and Majority Logic Based Implementations with Application to Nanotechnologies
Found in: VLSI Design, International Conference on
By Rui Zhang, Niraj K. Jha
Issue Date:January 2006
pp. 317-322
In this paper, we address the problem of state encoding of finite-state machines (FSMs) targeting threshold and majority logic based implementations, which have applications in nanotechnologies. Previous work on state encoding is based on Boolean logic. Th...
 
Towards a Responsive, Yet Power-ef.cient, Operating System: A Holistic Approach
Found in: Modeling, Analysis, and Simulation of Computer Systems, International Symposium on
By Le Yan, Lin Zhong, Niraj K. Jha
Issue Date:September 2005
pp. 249-257
<p>Although computing hardware has become increasingly more powerful, computer responsiveness is still an important issue due to multi-tasking and software bloat. We propose a holistic approach for improving computer responsiveness through user focus...
 
Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
Issue Date:March 2005
pp. 178-183
Security is emerging as an important concern in embedded system design. The security of embedded systems is often compromised due to vulnerabilities in
 
Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors
Found in: VLSI Design, International Conference on
By Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
Issue Date:January 2005
pp. 551-556
<p>Nanometer fabrication technologies have made it feasible to integrate multiple processors on a single chip. Heterogeneous multiprocessor systems-on-chip (MPSoCs), in which different processors are customized for specific tasks, can provide high le...
 
Thermal Modeling, Characterization and Management of On-Chip Networks
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Li Shang, Li-Shiuan Peh, Amit Kumar, Niraj K. Jha
Issue Date:December 2004
pp. 67-78
Due to the wire delay constraints in deep submicron technology and increasing demand for on-chip bandwidth, networks are becoming the pervasive interconnect fabric to connect processing elements on chip. With ever-increasing power density and cooling costs...
 
An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks
Found in: Computer Design, International Conference on
By Pallav Gupta, Rui Zhang, Niraj K. Jha
Issue Date:October 2004
pp. 540-543
We propose an automatic test pattern generation (ATPG) framework for combinational threshold networks. The motivation behind this work lies in the fact that many emerging nanotechnologies, such as resonant tunneling diodes (RTDs) and quantum cellular autom...
 
Automated Energy/Performance Macromodeling of Embedded Software
Found in: Design Automation Conference
By Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
Issue Date:June 2004
pp. 99-102
Efficient energy and performance estimation of embedded software is a critical part of any system-level design flow. Macromodeling based estimation is an attempt to speed up estimation by exploiting reuse that is inherent in the design process. Macromodeli...
 
Synthesis of Reversible Logic
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Abhinav Agrawal, Niraj K. Jha
Issue Date:February 2004
pp. 21384
A function is reversible if each input vector produces a unique output vector. Reversible functions find applications in low power design, quantum computing, and nanotechnology. Logic synthesis for reversible circuits differs substantially from traditional...
   
DESP: A Distributed Economics-Based Subcontracting Protocol for Computation Distribution in Power-Aware Mobile Ad Hoc Networks
Found in: IEEE Transactions on Mobile Computing
By Li Shang, Robert P. Dick, Niraj K. Jha
Issue Date:January 2004
pp. 33-45
<p><b>Abstract</b>—In this paper, we present a new economics-based power-aware protocol, called the <it>distributed economic subcontracting protocol</it> (DESP), that dynamically distributes task computation among mobile devic...
 
Profiling Driven Computation Reuse: An Embedded Software Synthesis Technique for Energy and Performance Optimization
Found in: VLSI Design, International Conference on
By Weidong Wang, Anand Raghunathan, Niraj K. Jha
Issue Date:January 2004
pp. 267
It has been observed that even highly optimized software programs perform
 
Dynamic Power Optimization of Interactive Systems
Found in: VLSI Design, International Conference on
By Lin Zhong, Niraj K. Jha
Issue Date:January 2004
pp. 1041
Abstract| Power has become a major concern for mobile computing systems such as laptops and handhelds, on which a significant fraction of software usage is interactive instead of computation-intensive. An analysis shows that over 90% of system energy and t...
 
Energy-Optimizing Source Code Transformations for OS-driven Embedded Software
Found in: VLSI Design, International Conference on
By Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
Issue Date:January 2004
pp. 261
The increasing software content of battery-powered embedded systems has fueled much interest in techniques for developing energy-efficient embedded software. Source code transformations have previously been considered for application software to reduce its...
 
A High-level Interconnect Power Model for Design Space Exploration
Found in: Computer-Aided Design, International Conference on
By Pallav Gupta, Lin Zhong, Niraj K. Jha
Issue Date:November 2003
pp. 551
In this paper, we present a high-level power model to estimate the power consumption in semi-global and global interconnects. Such interconnects are used for communications between logic modules, clock distribution networks, and power supply rails. The mai...
 
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